麻烦请教个问题，我在map时报出了这个错误ERROR PhysDesignRules:1461 - Incomplete PLL_ADV configuration. The signal
system_i/clock_generator_0/clock_generator_0/SIG_PLL0_CLKFBOUT on the CLKFBIN
pin of PLL_ADV comp
system_i/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_
inst is driven by the PLL_ADV CLKFBOUT pin therefore the COMPENSATION
attribute must be set INTERNAL, DCM2PLL, or PLL2DCM.
ERROR Pack:1642 - Errors in physical DRC.
不知道这个该如何解决？难得要修改*.MHS文件里面的CLK的属性？
我现在是把PLL模块产生的时钟信号输出到ISE中作为逻辑模块的时钟信号MHS的语句为
PORT sysclk = clk_66_6667MHz, DIR = O, SIGIS = CLK, CLK_FREQ = 66666666
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