KeyStone 的DDR3设计要求
This document provides implementationinstructions for the DDR3 interface incorporated in the Texas Instruments (TI)Keystone series of DSP devices. It supports 1333 MT/s and higher memory speedsin a variety of topologies (see to the Data Manual for supported speeds). Thisdocument assumes the user has a familiarization with DRAM implementationconcepts and constraints. When searching for a particular configuration see theappendix, which will alleviate the need for searching the entire document whichcontains all possible variations.
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