调试MIG的时候，MAP过程出现如下错误：ERRORPlace:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12
IO
IO_x
ERRORlace:382 - The placer was unable to find a feasible solution for the IOBs in your design. This is possibly due to
SelectIO banking constraints.
ERRORlace:418 - Failed to execute IOB Placement
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
我的UCF文件如下：
############################################################################
## File name : main.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx16-ftg256
## Speedgrade: -2
## Design Entry: VERILOG
## Design: with Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
############################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
############################################################################
## Clock constraints
############################################################################
NET "clk" TNM_NET = SYS_CLK;
TIMESPEC TS_SYS_CLK = PERIOD SYS_CLK3 50000 kHz;
############################################################################
NET "clk"
IOSTANDARD = "LVCMOS33" ;
NET "rst"
IOSTANDARD = "LVCMOS18" ;
NET "clk"
LOC = "T7" ;
NET "rst"
LOC = "F5" ;
############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq
" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;
############################################################################
# Status Signals
############################################################################
NET "calib_done"
IOSTANDARD = "LVCMOS33" ;
NET "calib_done"
LOC = "A5" ;
############################################################################
# I/O STANDARDS
############################################################################
NET "mcb3_dram_dq
" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_a
" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ba
" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
############################################################################
# MCB 3
############################################################################
NET "mcb3_dram_a[0]" LOC = "K5" ;
NET "mcb3_dram_a[1]" LOC = "K6" ;
NET "mcb3_dram_a[2]" LOC = "D1" ;
NET "mcb3_dram_a[3]" LOC = "L4" ;
NET "mcb3_dram_a[4]" LOC = "G5" ;
NET "mcb3_dram_a[5]" LOC = "H4" ;
NET "mcb3_dram_a[6]" LOC = "H3" ;
NET "mcb3_dram_a[7]" LOC = "D3" ;
NET "mcb3_dram_a[8]" LOC = "B2" ;
NET "mcb3_dram_a[9]" LOC = "A2" ;
NET "mcb3_dram_a[10]" LOC = "G6" ;
NET "mcb3_dram_a[11]" LOC = "E3" ;
NET "mcb3_dram_a[12]" LOC = "F3" ;
NET "mcb3_dram_ba[0]" LOC = "C3" ;
NET "mcb3_dram_ba[1]" LOC = "C2" ;
NET "mcb3_dram_ba[2]" LOC = "B1" ;
NET "mcb3_dram_cas_n" LOC = "H5" ;
NET "mcb3_dram_ck" LOC = "E2" ;
NET "mcb3_dram_ck_n" LOC = "E1" ;
NET "mcb3_dram_cke" LOC = "F4" ;
NET "mcb3_dram_dm" LOC = "J4" ;
NET "mcb3_dram_dq[0]" LOC = "K2" ;
NET "mcb3_dram_dq[1]" LOC = "K1" ;
NET "mcb3_dram_dq[2]" LOC = "J3" ;
NET "mcb3_dram_dq[3]" LOC = "J1" ;
NET "mcb3_dram_dq[4]" LOC = "F2" ;
NET "mcb3_dram_dq[5]" LOC = "F1" ;
NET "mcb3_dram_dq[6]" LOC = "G3" ;
NET "mcb3_dram_dq[7]" LOC = "G1" ;
NET "mcb3_dram_dq[8]" LOC = "L3" ;
NET "mcb3_dram_dq[9]" LOC = "L1" ;
NET "mcb3_dram_dq[10]" LOC = "M2" ;
NET "mcb3_dram_dq[11]" LOC = "M1" ;
NET "mcb3_dram_dq[12]" LOC = "2" ;
NET "mcb3_dram_dq[13]" LOC = "1" ;
NET "mcb3_dram_dq[14]" LOC = "R2" ;
NET "mcb3_dram_dq[15]" LOC = "R1" ;
NET "mcb3_dram_dqs" LOC = "H2" ;
NET "mcb3_dram_dqs_n" LOC = "H1" ;
NET "mcb3_dram_odt" LOC = "L5" ;
NET "mcb3_dram_ras_n" LOC = "J6" ;
NET "mcb3_dram_udm" LOC = "K3" ;
NET "mcb3_dram_udqs" LOC = "N3" ;
NET "mcb3_dram_udqs_n" LOC = "N1" ;
NET "mcb3_dram_we_n" LOC = "C1" ;
NET "mcb3_rzq" LOC ="M4";
NET "mcb3_zio" LOC = "M5" ;
这个错误是什么问题，应该如何解决？！ |
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