这里是STM32比较重要的头文件 我愛你的吻123原創講解 QQ:1746430162
typedef enum IRQn typedef enum表示定义了一个枚举型的数据结构,你可以用题目中的 IRQn 去定义变量
{系统异常ID:
标号 | 中断ID | 描述 | NonMaskableInt_IRQn | -14 | 不可屏蔽中断 | MemoryManagement_IRQn | -12 | Cortex-M3内存管理中断 | BusFault_IRQn | -11 | Cortex-M3 总线Fault中断 | UsageFault_IRQn | -10 | Cortex-M3 用法Fault 中断 | SVCall_IRQn | -5 | Cortex-M3 SV Call中断 | DebugMonitor_IRQn | -4 | Cortex-M3 调试监视中断 | PendSV_IRQn | -2 | Cortex-M3 Pend SV中断 | SysTick_IRQn | -1 | Cortex-M3 系统Tick中断 |
外设中断ID: 标号 | 中断ID | 描述 | 标号 | 中断ID | 描述 | WDT_IRQn | 0 | 看门狗 | EINT3_IRQn | 21 | 外中断3 | TIMER0_IRQn | 1 | 定时器0 | ADC_IRQn | 22 | AD转换 | TIMER1_IRQn | 2 | 定时器1 | BOD_IRQn | 23 | 欠压检测 | TIMER2_IRQn | 3 | 定时器2 | USB_IRQn | 24 | USB | TIMER3_IRQn | 4 | 定时器3 | CAN_IRQn | 25 | CAN | UART0_IRQn | 5 | UART0 | DMA_IRQn | 26 | 通用DMA | UART1_IRQn | 6 | UART1 | I2S_IRQn | 27 | I2S | UART2_IRQn | 7 | UART2 | ENET_IRQn | 28 | 以太网 | UART3_IRQn | 8 | UART3 | MCI_IRQn | 29 | SD/MMC卡I/F | PWM1_IRQn | 9 | PWM1 | MCPWM_IRQn | 30 | 电机控制PWM | I2C0_IRQn | 10 | I2C0 | QEI_IRQn | 31 | 正交编码接口 | I2C1_IRQn | 11 | I2C1 | PLL1_IRQn | 32 | PLL1锁存 | I2C2_IRQn | 12 | I2C2 | USBActivity_IRQn | 33 | USB活动 | Reserved0_IRQn | 13 | 保留 | CANActivity_IRQn | 34 | CAN活动 | SSP0_IRQn | 14 | SSP0 | UART4_IRQn | 35 | UART4 | SSP1_IRQn | 15 | SSP1 | SSP2_IRQn | 36 | SSP2 | PLL0_IRQn | 16 | PLL0锁存 | LCD_IRQn | 37 | LCD | RTC_IRQn | 17 | RTC | GPIO_IRQn | 38 | GPIO | EINT0_IRQn | 18 | 外中断0 | PWM0_IRQn | 39 | PWM0 | EINT1_IRQn | 19 | 外中断1 | EEPROM_IRQn | 40 | EEPROM | EINT2_IRQn | 20 | 外中断2 |
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/CMSIS中的中断定义
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt 非屏蔽中断 */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt Cortex-M3内存管理中断 */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMPER_IRQn = 2, /*!< Tamper Interrupt */
RTC_IRQn = 3, /*!< RTC global Interrupt */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
#ifdef STM32F10X_LD
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_LD */
#ifdef STM32F10X_LD_VL
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_LD_VL */
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