DSP与FPGA通信

只看该作者 · 2014-6-18 11:46

要实现TMS320F28335与FPGA内置RAM的通信，要用到DSP中外部扩展接口功能，我想问的是，外部扩展接口中LEAD,ACTIVE,TRIAL,该如何配置？

1万 · 2014-6-18 20:14

在手册的外部接口里详细讲述了.
分成无等待, 同步模式, 异步模式. 有详细的表格来描述这些设置以及时序图, 最好去仔细啃啃吧

2万 · 2014-6-18 22:16

我做过DSP5509A和FPGA的通信  用的是EMIF接口
只需要接CS，XWE,XRD就可以啦  不知你是怎么接的
参考一下代码多多找些XINTF相关的资料

Xintf初始化：
  // All Zones:
// Timing for all zones based on XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;  // XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.CLKOFF = 1; // DISABLE XCLKOUT
      XintfRegs.XINTCNF2.bit.WRBUFF = 0; // NO WRITE BUFFER
      XintfRegs.XINTCNF2.bit.CLKMODE = 1;  // XCLKOUT = XTIMCLK/2
      // Zone 0
      // Ignore XREADY for Zone 1 accesses
      // Change read access lead/active/trail timing
      XintfRegs.XTIMING0.bit.USEREADY = 0;
      XintfRegs.XTIMING0.bit.XSIZE = 3;             // ALWAYS WRITE TO 11BIT
      XintfRegs.XTIMING0.bit.XWRACTIVE = 3;
      XintfRegs.XTIMING0.bit.XWRTRAIL=7;
      XintfRegs.XTIMING0.bit.XWRLEAD=3;
      XintfRegs.XTIMING0.bit.XRDLEAD = 3;
      XintfRegs.XTIMING0.bit.XRDACTIVE =7;
      XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
      // Double lead/active/trial timing for Zone 1
      XintfRegs.XTIMING0.bit.X2TIMING=1;