EPwm3Regs.TBPRD = 1000; // 20kHz
EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
// EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
EPwm3Regs.CMPA.half.CMPA =1050;//80; // Setup compare
EPwm3Regs.CMPB = 1000;
EPwm3Regs.AQCTLA.all = 0x0218; // Force PWM1A to Low
EPwm3Regs.AQCTLB.all = 0x0018; // counter equal PRD,Force PWM3B output High |
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