实现FPGA内置RAM写数据线与读数据线合并，写地址与读地址线合并，附件中附图片，跪求大神指导，小弟感激不尽！~
module KINGSON6 (data,read_ram,write_ram,addr,read_addr,write_addr,write);
input [15:0] read_ram;
input write; //write(1),read(0)
output [15:0] write_ram;
inout [15:0] data;
output [10:0] write_addr;
output [10:0] read_addr;
input [10:0] addr;
reg [15:0] rdata1;
reg [15:0] rdata2;
reg [10:0] raddr1;
reg [10:0] raddr2;
always@(write or write_ram or read_ram or addr or data)
if(write)
begin
rdata1=data;
raddr1=addr;
end
else
begin
rdata2=read_ram;
raddr2=addr;
end
assign write_ram=rdata1;
assign data=rdata2;
assign write_addr=raddr1;
assign read_addr=raddr2;
endmodule
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