本帖最后由 52228254 于 2014-8-14 23:19 编辑
quartus12.1用IP核生成DDR3 SDRAM CONTROLLER WITH UNIPHY时编译出错
我用的是文件夹内的example
Error (129037): Output port OUTCLK on atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy", which is a stratixv_phy_clkbuf primitive, is driving one or more illegal destinations。 Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_write_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_mem_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal Error (129026): Output port OUTCLK of atom "ddr_0002:ddr_inst|ddr_pll0:pll0|uphy_clkbuf_memphy" is driving the I input port of atom "pll_c2p_write_clk~output", which is a stratixv_io_obuf primitive. This connection is illegal 有了解的大神吗。
芯片使用的是clconeV，型号5CEBA4U15I7N，DDR3是MT41J64M16，
这个是看到别人是这么解决的：首先例化的时候不能接后面几个PLL输出断口，然后编译第一步，再然后运行一次pin assignment脚本文件，然后全编译即可
可以看下这个人的回答：http://bbs.**thread-443186-1-1.html
但是我怎么都没看明白，求高人 |
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