本帖最后由 FBgg 于 2014-10-31 20:33 编辑
初学者,昨天刚得了块板子,还不会用,求牛牛们指教。
用的是BSP下面的例子
C:\Nuvoton\BSP Library\M451SeriesBSP_CMSIS_v3.00.003\SampleCode\NuEdu\Smpl_Basic01_7_Segment
不太清楚问题在哪里,希望得到大家指导,谢谢。
下面是按照网上说明对keil进行的设置。
Smpl_Basic01_7_Segment主程序
/**************************************************************************//**
* @file main.c
* @version V3.00
* $Revision: 2 $
* $Date: 14/08/12 6:35p $
* @brief Demonstrate how to set GPIO pin mode and use pin data input/output control.
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include "stdio.h"
#include "M451Series.h"
#include "NuEdu-Basic01.h"
#define PLL_CLOCK 72000000
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD(PD.6) and TXD(PD.1) */
SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD6MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);
SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD6MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
}
void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART module */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 baud rate */
UART_Open(UART0, 115200);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
int i, j;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
printf("Seven Segment Test\n\r");
Open_Seven_Segment();
Open_Seven_Segment();
while(1)
{
for(i = 0; i < 9; i++)
{
Show_Seven_Segment(i, 1);
for(j = 0; j < 500; j++)
CLK_SysTickDelay(1000);
}
for(i = 0; i < 9; i++)
{
Show_Seven_Segment(i, 2);
for(j = 0; j < 500; j++)
CLK_SysTickDelay(1000);
}
}
}
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