数据手册中还对供电去耦的相关内容进行了描述：
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps — 30 for the core supply and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product’s production lifetime needs to be considered.
接着还对JTAG的接口、启动模式（Bootmode）和复位相关的内容进行了描述。
（1）JTAG的接口
The TMS320C6713 DSP requires that both TRSTand RESETresets be asserted upon power up to be properly initialized. While RESETinitializes the DSP core, TRSTinitializes the DSP’s emulation logic. Both resets are required for proper operation. Note: TRSTis synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected after TRSTis asserted.While both TRSTand RESETneed to be asserted upon power up, only RESETneeds to be released for the DSP to boot properly. TRSTmay be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP’s emulation logic in the reset state. TRSTonly needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality.The TMS320C6713 DSP includes an internal pulldown (IPD) on the TRSTpin to ensure that TRSTwill always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRSThigh. However, some third-party JTAG controllers may not drive TRSThigh but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRSTto initialize the DSP after powerup and externally drive TRSThigh before attempting any emulation or boundary scan operations.Following the release of RESET, the low-to-high transition of TRSTmust be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. Note: The DESIGN−WARNING section of the TMS320C6713 BSDL file contains information and constraints regarding proper device operation
while in Boundary Scan Mode. For more detailed information on the C6713 JTAG emulation, see the TMS320C6000 DSP Designing for JTAG Emulation Reference Guide(literature number SPRU641).
（2）启动模式
The C6713 has three types of boot modes:
Host boot
If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
Emulation boot Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development. EMIF boot (using default ROM timings)Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. The boot process also lets you choose the width of the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is
released from the “stalled” state and start running from address 0.
（3）复位
A hardware reset (RESET) is required to place the DSP into a known good state out of power−up.The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held low during power−up.Prior to deasserting RESET(low−to−high transition), the core and I/O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency.
再接着数据手册的后面就是一些相关的时序，在编程时尤为关键，但不是现在考虑的问题；最后就是机械封装结构了，PCB封装的绘制主要参考数据手册结尾处的机械封装描述。
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