CY7C63813做的PS2鼠标键盘通信过程丢失数据
01. PS2M_Send:
02._PS2M_Send:
03..data: equ -1 ; Local stack variables
04..cnt: equ -2
05..parity: equ -3
06.; M8C_DisableGInt
07. PUSH X ; Build the local variable
08. ADD SP, 3 ;
09. MOV X, SP ;
10. MOV [X + .data], A ; Save off the data byte
11. MOV [X + .parity], 1 ; Start the parity at 1
12. MOV [X + .cnt], 8 ; Send 8 data bits
13. MOV [_fHostRqs], 0
14.; Test for inhibit
15. TST REG[PS2M_DR], PS2M_SCLK ; Inhibit?
16. JZ .rts ; Continue to wait if we are inhibited
17.
18. DELAY 20, 60 ; Min delay between check for inhibit
19.
20. TST REG[PS2M_DR], PS2M_SCLK ; Inhibit?
21. JZ .rts ; Continue to wait if we are inhibited
22.
23.; Test for RTS
24. TST REG[PS2M_DR], PS2M_SDATA ; RTS?
25. JZ .rts ; Jump if RTS
26.; change data pin to output mode
27. OR REG[P01CR], 0x01
28. OR REG[P02CR], 0x01 ;test debug
29.; Flow here to send start bit
30. CALL PS2M_Send_0 ; Start bits are zero
31. JC .inhib ; Host has inhibited
32.
33. DELAY 2, 12 ; Wait 2 uSec
34.
35.; Flow or jump here to sent the data bits
36..snb:
37. ASR [X + .data] ; rotate the next bit to the carry
38. JC .s1 ; and send a 1 or 0 based
39..s0:
40. CALL PS2M_Send_0 ; Send 0
41. JMP .cont
42..s1:
43. INC [X + .parity] ; Count the number of 1 bits for the parity
44. CALL PS2M_Send_1 ; Send 1
45..cont:
46. JC .inhib ; Did the host inhibit us during the last bit?
47. DEC [X + .cnt] ; If not, send the next bit
48. JZ .s_parity ; When it hits zero, do the parity
49. JNC .snb ; It will carry after the parity bit is sent
50.
51.; Flow here to send the stop bit
52. CALL PS2M_Send_1 ; Stop bits are 1
53. JMP .success
54.
55.; Flow here after all 8 data bits have been clocked out
56..s_parity:
57. MOV A, [X + .parity] ; clock out the lsb of the parity
58. MOV [X + .data],a ; Save the data
59. JMP .snb
60.
61.; Jump here on a successful stop bit
62..success:
63. MOV A, 0 ; Flow here after a successful stop bit
64.; CMP [PS2M_bCmdCnt], 0x00
65.; JZ .exit
66.; CALL PS2M_ReadSendBuffer
67. JMP .exit
68.; Jump here if we failed because we were inhibited
69..inhib: ; Jump here for any failed bit
70. OR reg[PS2M_DR], PS2M_CLKH_DATAH
71. MOV [_fHostRqs], 1
72. MOV A, 0x88
73. JMP .exit
74.; Jump here if we found a RTS
75..rts: ; Jump here for a RTS
76. MOV A, 0x90 ;
77.; Jump or flow here to exit
78..exit:
79. ;change data pin to input mode
80. AND REG[P01CR], 0xfe
81. AND REG[P02CR], 0xfe ;test debug
82. ADD SP, -3 ; Clean up the stack
83. POP X
84.; M8C_EnableGInt
85. PUSH A
86. DELAY 38, 12 ; Wait 38 uSec
87. POP A
88. RET
89.;-----------------------------------------------------------------------------
90.; FUNCTION NAME: PS2M_Send_1, PS2M_Send_0
91.; DESCRIPTION: Local function. Assembly interface only.
92.;
93.;-----------------------------------------------------------------------------
94.;
95.; ARGUMENTS:
96.;
97.; RETURNS:
98.;
99.; SIDE EFFECTS: REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
100.;
101.; THEORY of OPERATION or PROCEDURE:
102.;
103.;-----------------------------------------------------------------------------
104.PS2M_Send_1:
105. OR REG[PS2M_DR], PS2M_SDATA ; Set the data bit high
106. DELAY 10, 12 ; Wait 10 uSec
107. ; Clock Low ; Clock Low and the data
108. AND REG[PS2M_DR], ~PS2M_SCLK ; Clock Low
109. DELAY 38, 12 ; Wait 38 uSec
110. ; Clock High ; Finally Clock High and the data
111. OR REG[PS2M_DR], PS2M_SCLK ; Clock High
112. DELAY 22, 60 ; Wait 22 uSec
113. ; Check for inhibit
114. CLEARC ; Carry clear indicates success
115. AND REG[P02CR], 0xfe ;test debug
116. TST REG[PS2M_DR], PS2M_SCLK ; Inhibit?
117. JNZ .clock_done ; Jump if not
118. SETC ; Carry set indicates fail/Inhibit
119..clock_done:
120. ; Done
121. OR REG[P02CR], 0x01 ;test debug
122. RET
123.
124.
125.
126.PS2M_Send_0:
127. AND REG[PS2M_DR], ~PS2M_SDATA ; clear the data bit high
128. DELAY 10, 12 ; Wait 10 uSec
129. ; Clock Low ; Clock Low and the data
130. AND REG[PS2M_DR], ~PS2M_SCLK ; Clock Low
131. DELAY 38, 12 ; Wait 38 uSec
132. ; Clock High ; Finally Clock High and the data
133. OR REG[PS2M_DR], PS2M_SCLK ; Clock High
134. DELAY 22, 60 ; Wait 22 uSec
135. ; Check for inhibit
136. CLEARC ; Carry clear indicates success
137. AND REG[P02CR], 0xfe ;test debug
138. TST REG[PS2M_DR], PS2M_SCLK ; Inhibit?
139. JNZ .clock_done ; Jump if not
140. SETC ; Carry set indicates fail/Inhibit
141..clock_done:
142. ; Done
143. OR REG[P02CR], 0x01 ;test debug
144. RET
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