本帖最后由 free_tend 于 2014-11-21 13:43 编辑
imx6q uboot-2009.8 LVDS:TM104SDH01
求助， uboot无法显示开机LOGO：
以前的lvds的屏幕是支持uboot显示logo的,换成这块屏之后，要修改频率，因为支持是30M到50M.
static struct fb_videomode lvds_xga = {
"TM104SDH01", 60, 800, 600, 25000, 100, 100, 10, 10, 56, 8, 0,
FB_VMODE_NONINTERLACED, FB_MODE_IS_DETAILED,
};
linux内核启动后显示图像是没有问题的,上面的参数就是从内核中来的.
尝试对比uboot和内核中ipu 和下面代码中的寄存器, 得到的结果是都一样.
用示波器测量lvds的clk也是40M，每个通道也有数据.
/*
* ipu1_pixel_clk_x clock tree:
* osc_clk(24M)->pll2_528_bus_main_clk(528M)->
* pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
* ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
*/
/* pll2_pfd_352M */
/* disable */
writel(0x1 << 7, ANATOP_BASE_ADDR + 0x104);
/* divider */
writel(0x3F, ANATOP_BASE_ADDR + 0x108);
//writel(0x15, ANATOP_BASE_ADDR + 0x104);
writel(0x22, ANATOP_BASE_ADDR + 0x104); <-----------------主要修改了这个值 528 * 18 /34
/* ldb_dix_clk */
/* source */
reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
reg &= ~(0x3F << 9);
reg |= (0x9 << 9);
writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
/* divider */
reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
reg |= (0x3 << 10);
writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
/* pll2_pfd_352M */
/* enable after ldb_dix_clk source is set */
writel(0x1 << 7, ANATOP_BASE_ADDR + 0x108);
/* ipu1_di_clk_x */
/* source */
reg = readl(CCM_BASE_ADDR + CLKCTL_CHSCCDR);
reg &= ~0xE07;
reg |= 0x803;
writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
.......
ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666,
DI_PCLK_LDB, 40000000);
Head file define :
#define CONFIG_SPLASH_SCREEN
uboot settings:
setenv splashimage ‘0x27f00000’
setenv splashpos ‘0,0’
setenv lvds_num 1
以前的号忘记密码了，所以这个没积分了, |
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