本帖最后由 jlrhw 于 2015-2-6 12:09 编辑
原程序
module SPI(MCUWR,SPICLK,MCUDO,MCUDI,SPICS,SPIstart,rxdDATA);
input MCUWR,SPICLK,SPICS,SPIstart,MCUDO; //收发转换（高电平接收）,SPI时钟,SPI使能,SPI复位,单片机发送
output MCUDI,rxdDATA; //单片机接收，接收缓存
reg MCUDI;
reg [9:0] rxdDATA; //接收缓存
reg [6:0] Cnt;
always @ (negedge SPICLK or negedge SPIstart)
if(!SPIstart) //SPI复位信号
begin
Cnt<=6'd0;
rxdDATA<=0;
end
else
begin
if(!SPICS) //SPI低电平使能
begin
if(MCUWR) //切换为CPLD接收
begin
Cnt<=Cnt+1'b1;
case(Cnt)
2'd0:
rxdDATA[0]<=MCUDO;
2'd1:
rxdDATA[1]<=MCUDO;
2'd2:
rxdDATA[2]<=MCUDO;
2'd3:
rxdDATA[3]<=MCUDO;
2'd4:
rxdDATA[4]<=MCUDO;
2'd5:
rxdDATA[5]<=MCUDO;
2'd6:
rxdDATA[6]<=MCUDO;
2'd7:
rxdDATA[7]<=MCUDO;
2'd8:
rxdDATA[8]<=MCUDO;
endcase
end
end
end
endmodule
测试程序：
`timescale 1 ps/ 1 ps
module SPI_vlg_tst();
reg MCUDO;
reg MCUWR;
reg SPICLK;
reg SPICS;
reg SPIstart;
wire MCUDI;
wire [9:0] rxdDATA;
reg k;
reg [6:0] testcnt;
SPI i1 (
.MCUDI(MCUDI),
.MCUDO(MCUDO),
.MCUWR(MCUWR),
.SPICLK(SPICLK),
.SPICS(SPICS),
.SPIstart(SPIstart),
.rxdDATA(rxdDATA)
);
initial
begin
testcnt<=0;
SPIstart = 1;
#10 SPIstart = 0;
#30 SPIstart = 1; //产生SPI复位信号
end
initial
begin
SPICS = 1;
#30 SPICS = 0; //产生SPI使能信号
end
initial
begin
MCUWR = 0;
#30 MCUWR = 1; //产生CPLD接收使能信号
end
initial
begin
SPICLK = 0;
#50
for(k=0;k<29;k=k+1)
begin
#10 SPICLK = ~SPICLK; //产生SPI时钟信号
end
end
always @ (posedge SPICLK)
begin
testcnt<=testcnt+1'b1;
case(testcnt)
6'd0:
begin
MCUDO<=1'b1;
end
6'd1:
begin
MCUDO<=1'b1;
end
6'd2:
begin
MCUDO<=1'b0;
end
6'd3:
begin
MCUDO<=1'b1;
end
6'd4:
begin
MCUDO<=1'b1;
end
6'd5:
begin
MCUDO<=1'b1;
end
6'd6:
begin
MCUDO<=1'b0;
end
6'd7:
begin
MCUDO<=1'b0;
end
6'd8:
begin
MCUDO<=1'b0;
end
endcase
end
endmodule
从MODELSIM仿真出的波形来看，rxdDATA[5]，rxdDATA[6]在testcnt为5和6时分别应该为高电平，可仿真结果 却一直是低电平，恳请各位高手帮我分析下，代码是否有什么问题
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