手册里面的两段描述：
PLL Lock Time
The lock time is the time required for PLL output stabilization. The lock time should be bigger than 208us. After reset
and wake-up from STOP and SL_IDLE mode, respectively, the lock-time is inserted automatically by the internal
logic with lock time count register. The automatically inserted lock time is calculated as follows;
PLL is turned on only when SLOW_BIT is 1.
After PLL stabilization time (minimum 150uS), SLOW_BIT
may be cleared to 0. |
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