在str71x的hdlc的测试程序中，用timer2为hdlc配置时钟，其中有几处不清楚。请教了。程序如下void clks_init(void)
{
RCCU_Div2Config (ENABLE); //OSC input is divide by 2
RCCU_PLL1Config(RCCU_PLL1_Mul_12, RCCU_Div_2); //RCLK = 48MHz
RCCU_RCLKSourceConfig (RCCU_PLL1_Output);
RCCU_MCLKConfig(RCCU_DEFAULT); //MCLK=48MHz
RCCU_PCLKConfig(RCCU_Div_2); //PCLK2=24MHz APB2 periph
RCCU_FCLKConfig(RCCU_Div_2); //PCLK1=24MHz APB1 periph (fast)
RCCU_PLL2Config(RCCU_PLL2_Mul_12, RCCU_Div_2); //configure PLL2 for HDLC clock
//setup timer2 (P0.13) for external HDLC clock connected to HCLK
TIM_ClockSourceConfig (TIM2, TIM_INTERNAL );
TIM_PrescalerConfig (TIM2,10 ); //24Mhz/77 = 312KHz
TIM_PWMOModeConfig (TIM2,0x7,TIM_LOW,0x7,TIM_HIGH); //square wave output
TIM_CounterConfig(TIM2, TIM_START);
}
我的问题是为什么倒数第三句TIM_PrescalerConfig (TIM2,10 ); //24Mhz/77 = 312KHz
的注释中是对24m分频，应该是48m对么？
在主函数中：//***************** Test 2 External clocking, print receive buffer*********************
//External clock (155.8kHz) on PLL2 input HCLK
HDLC_XmitClockSourceConfig(HDLC_HTXCKSource);//写波特率的RCKS
HDLC_XmitBaudrateConfig(0);
HDLC_RecvClockSourceConfig(HDLC_HRXCK);//写预频分因子rcks
HDLC_RecvClockPrescalerConfig(0);//写预分频因子prs
问题是：//External clock (155.8kHz) on PLL2 input HCLK这句注释看不懂
还有：RCCU_Div2Config (ENABLE); //OSC input is divide by 2这句能理解，但是注释里面用osc？对么？osc不是32k？ |
|
楼主
标题置顶
标题高亮
