程序如下：library IEEE;
use IEEE.stD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY faguangerjiguan IS
PORT
(q:OUT STD_LOGIC_VECTOR (0 DOWNTO 7);
clk: IN BIT
);
END ENTITY faguangerjiguan;
ARCHITECTURE hbv of faguangerjiguan IS
signal clk0:stD_LOGIC;
BEGIN
PROCESS(clk)
VARIABLE count:INTEGER:=0;
BEGIN
if clk'event and clk='0' then
count:=count+1;
if count=25000000 then count:=0;clk0<=not clk0;
end if;
end if;
END PROCESS;
PROCESS(clk0)
VARIABLE m:STD_LOGIC_VECTOR (0 DOWNTO 7):="01111111";
BEGIN
if clk'event and clk='0' then
m:=m(0)& m(1 DOWNTO 7);
end if;
q<=m;
END PROCESS;
END ARCHITECTURE hbv;
错误如下：
1.Error (10324): VHDL Expression error at faguangerjiguan.vhd(28): expression ""01111111"" has 8 elements ; expected 0 elements.
2.Error: Can't elaborate top-level user hierarchy
3.Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 232 megabytes
Error: Processing ended: Sat Jul 02 16:42:54 2016
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00
4.Error: Quartus II Full Compilation was unsuccessful. 4 errors, 2 warnings
求大神帮忙改一下。并将流水灯改为从下往上的形式。跪谢！！！！！！！！ |
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