Protel Design System Design Rule Check<br />PCB File : DocumentsPCB1.PCB<br />Date : 7-Mar-2009 <br />Time : 21:02:31<br /><br />Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (Disabled)(On the board )<br />Rule Violations :0<br /><br />Processing Rule : Width Constraint (Min=10mil) (Max=20mil) (Prefered=20mil) (On the board )<br />Rule Violations :0<br /><br />Processing Rule : Room Sheet1 (Region = (-260mil, 203.238mil, -259.989mil, 2328.188mil) (has footprint 0805 And Is part of Component class All Components And Is in component C1 )<br /> Violation between Component C1(49560mil,49700mil) TopLayer and <br /> Room Sheet1 (Region = (-260mil, 203.238mil, -259.989mil, 2328.188mil) (has footprint 0805 And Is part of Component class All Components And Is in component C1 ) <br />Rule Violations :1<br /><br />Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )<br />Rule Violations :0<br /><br />Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )<br />Rule Violations :0<br /><br />Processing Rule : Broken-Net Constraint ( (On the board ) )<br />Rule Violations :0<br /><br />Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )<br />Rule Violations :0<br /><br /><br />Violations Detected : 1<br /> |
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