Problems with SPI (PSoC3)

只看该作者 · 2010-5-24 22:12

本帖最后由 san_gr 于 2010-5-25 16:35 编辑

Hi everyone.

First of all I am sorry that i write in english but I don't speak or understand Chinese AT ALL! :) So I hope I didn't break any of the forum's rules.

I am an engineering student in Denmark and I am currently working on a PSoC3 project. I have already asked at the english PSoC forums and at Cypress directly but I haven't received a satisfactory answer. That is why I want to ask you also. So here it goes:

I am working on a big project where I will have 9 PSoC3 devices working together.

A short description of the project:
8 PSoC3 devices to "read", amplify, filter and store locally 8 analog sensors.
1 PSoC3 device to be the master SPI and control the rest.

The master has to periodically acquire the data gathered from the 8 slaves and store them on an SD Card. Hopefully the SPI has to transmit with a bit rate of 8 MHz.

The problem:
For weeks now I am trying to establish a solid SPI communicationbetween 2 PSoC3 chips using two CY8CKIT-001 kits. I have tried havingDMAs and/or ISRs to transfer the data from and to SPI, I have tried tojust send 4 bytes from each side with the APIs but all my attempts havefailed. Almost every time I get wrong bytes (very few times I got the correct ones).

The latest attempt I'm doing is having a simple communicationprotocol. So the Master tries to send a command and the Slave has toreturn a reply according to the command. This gives me correct resultsmore often than before but still 1 out of 4 times Ireceive wrong results.

I have thoroughly studied both "SPI Master and Slave in Loopback"and "SPI with DMA" application notes and they seem to work perfectly onmy Development Kit.

I am pretty sure I am missing something but I can't find out whatit is. So I would greatly appreciate it if you could take a look in myproject and point out any possible mistakes I have made.

I have attached the workspace. It has two projects, "Master4" and "Slave4". Each project is used on one of the two CY8CKIT-001 kits.

Thank you in advance! And please reply in English :P

Regards,
Stefanos

PS. Hereyou can find my post to the English forum which has details of my previous attempts with the SPI.

只看该作者 · 2010-5-24 22:13

咋全英文的~~~

只看该作者 · 2010-5-24 22:28

sorry~~~

只看该作者 · 2010-5-24 22:29

来自Denmark的朋友，得版主出山了

只看该作者 · 2010-5-24 22:48

This is from a friend of mine:
各位好。我是stefanos的中国朋友，如果各位谁能够给他支上个招也可以用中文回帖，我会帮他翻译解释。谢谢大家～～～

只看该作者 · 2010-5-25 13:46

I am studying PSoC1 recently，and I have no idea about PSoC3,but I think there are some problems in the Function "Stef_SPI_GetReply ()":
such as:
SPIM_WriteByte(0xFF); //send empty byte in order to receive a byte from slave
while(!(SPIM_ReadStatus() & SPIM_STS_TX_FIFO_EMPTY));
//wait for the byte to be transmitted
temp2 = SPIM_ReadByte(); //read the incoming byte
The macro SPIM_STS_TX_FIFO_EMPTY means the Tx Buffer is empty or the Transmition is completed,if it only means empty(that is to say the data is puted into the shift reg and ready to be transmited ,but not completed),and then you call SPIM_ReadByte(),It is hard to get the correct result,because cpu is much quicker than SPI.

只看该作者 · 2010-5-25 13:52

and also there is anather problem will hanppen in your design:
The master do not know when the slave gets the return-data ready.

只看该作者 · 2010-5-25 16:32

Hi,
Thanks for the response. The documentation is not very clear on SPIM_STS_TX_FIFO_EMPTY so maybe you are right. Maybe I should try SPIM_STS_BYTE_COMPLETE instead. I will try it tomorrow.
The reason I used SPIM_STS_TX_FIFO_EMPTY is because Cypress is using it in one of the example projects.

I know that the master does not know when the slave gets the return data ready and that is why I ask from the slave to send also a start and end byte:

0x0F //start byte
response
0xF0 //end byte

So I read and discard data until I receive 0x0F. Then the next byte should be the response and to be sure that it was not random I have to receive a 0xF0 at the end.

I thought of using a DATA_READY pin that would go high when the slave has data to be sent, but I don't have enough ports for all slaves.

If you have any better ideas I'll be happy to hear it :)

只看该作者 · 2010-5-25 22:57

In my opinion, the macro SPIM_STS_TX_FIFO_EMPTY means the Tx buffer is empty(at least for PSoC1),but you should let  master supply clk to get data from slave after the transmition is over(It's better that there is some delay for your test:)).
I think your got misunderstanding about the master getting data time(and there maybe some
misunderstanding  for me about your design:lol).
1st:I think each slave has its main job to do,so it can't wait all the time,and then there maybe timegap between the slave spi  gotton one byte and the slave cpu getting the byte to handle.
How do the master konw the gap ?
2nd:There may be interrupts happen between the slave gotton 0x0F and your response.The master maybe also do not konw.
I think DATA_READY pin to trigger master GPIO_interrupt is a good method,one GPO is enough in theory.Have you used all GPIO?
you can also use IIC or UART+RS485 instead of SPI.
I am also newer for PSoC,u can mail me by zhryhfut@163.com

只看该作者 · 2010-5-28 16:30

In my opinion, the macro SPIM_STS_TX_FIFO_EMPTY means the Tx buffer isempty(at least for PSoC1),but you should let master supply clk to getdata from slave after the transmition is over(It's better that there issome delay for your test:)).

You were right about TX_FIFO_EMPTY. I found out that it means last byte in the shift register, but that doesn't mean it is transmitted. So I changed it to BYTE_COMPLETE. But again it didn't work correctly.
But...
I hooked up an oscilloscope and found out that often the Slave sends the bits shifted to the right.
So instead of: 11110000 //0xF0
The slave sends: 01111000 //0x78

That's why the master returns an UNEXPECTED_ERROR.

Both master and slave are set to mode 3 (11) with MSB first.

Any thoughts?

I think each slave has its main job to do,so it can't wait all thetime,and then there maybe timegap between the slave spi gotton onebyte and the slave cpu getting the byte to handle.
How do the master konw the gap ?

For now I am just trying to make a successful transfer between the 2 devices. If it works I am going to have an interrupt from the SPI.

There may be interrupts happen between the slave gotton 0x0F and your response.The master maybe also do not konw.
I think DATA_READY pin to trigger master GPIO_interrupt is a good method,one GPO is enough in theory.Have you used all GPIO?
you can also use IIC or UART+RS485 instead of SPI.

In my initial design I had used up all the ports. I actually had only 1 free port :) But now I am going to change the design and have A LOT more free ports. So I plan to use a DATA_READY pin.

But it is useless if we can not solve the first problem ;)

只看该作者 · 2010-5-28 16:52

哇，全英文的:funk:

只看该作者 · 2010-5-28 19:39

哇，全英文的:funk:
happytiger2010 发表于 2010-5-28 16:52

對不起

Hi everyone.

First of all I am sorry that i write in english but I don't speak or understand Chinese AT ALL! :)
san_gr 发表于 2010-5-24 22:12

This is from a friend of mine:
各位好。我是stefanos的中国朋友，如果各位谁能够给他支上个招也可以用中文回帖，我会帮他翻译解释。谢谢大家～～～
san_gr 发表于 2010-5-24 22:48

1万 · 2010-5-28 20:29

意思好懂，但是问题不简单