Common Sense Frequency Synthesis频率合成技术常识
By Erik Mentze， Sr. Systems Engineer， Cypress Semiconductor
作者：Erik Mentze，高级系统工程师，赛普拉斯半导体
Configuring a Phase Locked Loop (PLL) for a given frequency synthesis application can be， at the same time， both a quick and easy process as well as a time consuming， tedious， and iterative process.
After determining a set of frequency synthesis parameters that meet the system needs， however， there is always the doubt: did I choose the best possible frequency synthesis parameters?
Perhaps there is a different set that will run cleaner and consume less power or have more margin.
It is these design choices that this paper will attempt to shed some common sense design principles upon.
对于给定的频率合成技术来说，其应用都可以相应地配置一个锁相环（PLL），它是一个快速和容易的步骤，同时，又是一个耗时的，乏味的，反复的过程。在确定一组满足系统的需要的频率合成技术参数后
，经常会有这样的疑问：我有没有选择最好的频率合成技术参数？可能还有另外的设置可以使频率更干净、电源消耗更少、或者有更多的余量。正是这些设计选择，本文将试图摆脱一些通常设计原则。
An Overview of PLL Frequency Synthesis锁相环频率合成技术概述
At the most fundamental level， the goal of any frequency synthesizer is， based on a given reference frequency， to generate a desired output frequency by inserting divide blocks between the reference oscillator and the output clock and using a feedback loop with a phase detector to maintain phase coherence.
Figure 1 shows the general form of a charge pump integer divide phase locked loop (a very common topology used for frequency synthesis).
最基本的情况是这样的，任何频率合成器的目标是，基于一个给定的参考频率，通过在参考时钟和输出时钟之间插入分频器模块，来产生一种期望的输出频率，并使用一个带相位检测器的反馈回路来维持相位一致。图1指出了整数分电流泵锁相环的一般形式(用于频率合成技术的很常见的拓扑结构)。
Figure 1.
Block diagram of a basic integer divide PLL.图1.基本整数分频锁相环框图 | |
The three divide blocks – the reference divider (Q)， the feedback divider (P)， and the output divider (N) – define the gross functionality of the loop and must be chosen to set the desired output frequency.
One common way of determining these values is to divide the output frequency by the reference frequency， and reduce the fraction:
三分频器模块-参考分频器(Q)，回馈分频器(P)，输出分频器(N)-定义环路总功能，必须选择为预期的输出频率。通常确定这些值的方式是输出频率除以参考频率，略去小数点后面的数。
The difficulty in solving this equation is that there are three degrees of freedom and so the most common technique for solving it is to use a search algorithm.
Such algorithms work by searching the solution space， looking for sets of P， Q， and N values that will result in the desired frequency result.
该方程求解的困难是，有三个变量，所以最常见的解决方式是使用搜索算法。这种算法通过搜索区间内解，找到适合的P，Q和N值，这就是期待的频率结果。
An additional configuration that is commonly used in programmable SoCs is to have multiple output dividers.
This allows for the synthesis of multiple outputs at different frequencies.
It is important to note that each output is an integer multiple of the VCO frequency.
This topology emphasizes the importance of selecting the right VCO frequency so as to maximize the number of system clocks that can be generated off of the single PLL.
在可编程片上系统里通常用的附加配置可以有多个输出分频器。这也可合成多个不同输出频率。还有很重要的一点是，每个输出都是压控振荡器频率的整数倍。这种方式强调了选择正确的压控振荡器的重要性，从而最大限度地提高了从一个锁相环产生的系统时钟的数量。
An Illustrative Example举一个例子
For this example， we will synthesize a 50MHz output from a 14.3181818…MHz reference (a common video frequency).
Assume the VCO has a frequency range of 100MHz to 400MHz.
Using a search algorithm， we can determine the possible N divide values and use the corresponding VCO frequencies to determined Q and P values.
All results for N values 2-8 are shown in Table 1.
This is the complete set of frequency synthesis parameters that are possible given our reference frequency and desired output frequency.
在这个例子中，我们将从14.3181818…MHz 参考时钟(一种常见的视频频率)合成一个50MHz输出。假设压控振荡器的频率范围是100MHz - 400MHz。使用搜索算法，我们可以确定可能的N分频值并使用相应的压控振荡器频率来确定Q和P值。对于N值在2 – 8之间的所有结果都显示在表1。这是完整的一套鉴于我们参考频率和期望输出频率的可能的频率合成参数。
Table 1.
Summary of Example Results | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
Now that we have confidently found the set of all possible frequency synthesis parameters that meet our needs， we can turn our attention to selecting the performance parameters.
Several common parameters that are optimized in various applications are:
现在我们找到了所有可能的满足我们需求的频率合成参数，我们可以将我们的注意力放到选择性能好的参数上。在不同应用中，通常有下面几种参数需要优化:
Power
Power is dominated by the VCO frequency， charge pump current， and divide block settings.
Most VCO architectures require larger tail currents to achieve higher frequencies.
So as frequency increases， so does power consumption.
Charge pump current is discharged once for each PFD period.
When larger charge pump currents are required (for loop stability or fast startup / settling time) more power is consumed per PFD period.
Clock dividers dissipate power at each clock edge.
Larger clock divide values require more divide cells to transition， consuming more power.
功耗
功耗受控于压控振荡器的频率、电流泵电流、分频器模块设置。大多数压控振荡器结构需要比较大的尾电流以达到更高的频率。所以随着频率的增加，功率消耗也会提高。电流泵电流每个PFD时期放电一次。当需要较大的电流泵电流时(循环稳定或快速启动/设置时间)，每个PFD时期会有更多的功耗。时钟分频器在每个时钟沿消耗功率。时钟分频器值越大，就需要更多的分频器单元来传输，这就消耗了更多的功率。
Startup Time / Settling Time
The startup and settling time for a charge pump PLL is dominated by the loop natural frequency.
This parameter can be thought of as the frequency slew rate of the PLL.
It quantifies how fast the PLL can change the output frequency.
It is proportional to the VCO gain and charge pump current， and inversely proportional to the feedback divide value and loop filter capacitance.
Since the PLL output frequency is set by the VCO frequency， when we want to force a large step in the output frequency (either from zero at startup or from one setting to another) we need to force a large step in the VCO control voltage.
This is accomplished by the charge pump dumping a large amount of charge onto the loop filter cap.
The amount of frequency change per volt increase on the loop filter is set by the VCO gain.
The rate at which the loop filter voltage is updated is set by the PFD frequency.
启动时间/设置时间
一个电流泵锁相环的启动和设置时间是由固有循环频率决定的。该参数可以视为是速度慢了的锁相环频率。它来量化锁相环可以改变输出频率的速度。它和压控振荡器增益和电流泵电流是成正比的，和反馈分频器值和环路滤波电容是成反比的。既然锁相环输出频率是由压控振荡器频率设置的，那么当我们希望输出频率步幅大时(无论是启动时从零开始还是从一种设置到另外一个设置)我们就需要压控振荡器控制电压有一个大步幅。这是由电流泵流出大量电荷到环路滤波电容来完成的。环路滤波器上每伏特频率变化量是由压控振荡器增益设定的。环路滤波器电压的更新速率由PFD频率设定的。
Jitter (Cycle-to-Cycle)
Cycle-to-Cycle jitter (the change in period length from one period to the next) can easily be dominated by the individual blocks of the PLL (VCO， dividers， reference oscillator)， creating a situation where no loop parameter changes can improve performance.
If you are working with a low noise PLL， then loop parameter settings can make a significant improvement.
Similar to startup time / settling time， the PFD frequency and VCO gain play a key role.
Higher PFD frequencies mean that the PLL loop filter voltage is refreshed at a higher rate.
This prevents the loop filter voltage from drifting.
By using a large loop filter capacitance， the amount of voltage drift per PFD period is minimized.
Because the VCO gain dictates how far the output frequency drifts per unit voltage drift on the loop filter， lower VCO gain makes the PLL less sensitive to loop filter voltage drift.
抖动(Cycle-to-Cycle)
Cycle-to-Cycle 抖动(一个周期到下一个周期的周期长度变化)能很容易地由锁相环的分立块体控制 (压控振荡器，分配器，参考振荡器)，建立没有循环参数变化的情况可以提高性能。如果使用低噪音锁相环，那么环路参数设置可以显著提高性能。
类似于启动时间/设置时间，PFD频率和压控振荡器增益在其中扮演了关键角色。更高PFD频率意味着锁相环环路滤波器电压刷新频率较高。这就防止了环路滤波器电压漂移。使用大的环路滤波电容，
每PFD周期电压漂移量会降低到最小程度。因为压控振荡器增益决定了环路滤波器每单元电压漂移对应的输出频率漂移量，压控振荡器增益越低，锁相环对环路滤波器电压漂移越不敏感。
Phase Noise
Optimizing phase noise is highly application dependent， but a few general observations can be made.
Phase noise contributed by the reference oscillator can be suppressed by setting the PLL to a lower closed loop bandwidth.
Phase noise contributed by the VCO can be suppressed by setting the PLL to a higher closed loop bandwidth.
Phase noise divides down proportional to the output divide setting.
If the output divider is a low noise divider， then running the VCO at a higher frequency and dividing the output frequency down will result in a phase noise improvement.
相位噪声
优化相位噪声和应用关系密切，大体观察就能看到。由参考振荡器引起的相位噪声，可以通过将锁相环设置为较低的闭环带宽方式来减小。由压控振荡器引起的相位噪声，可以通过将锁相环设置为较高的闭环带宽方式来减小。
相位噪声分频器下降和输出分频器设置成正比。如果输出分配器是低噪声分压器，那么压控振荡器的就运行在较高的频率，并将输出频率降低来使相位噪声得到改进。
Optimizing the Illustrative Example优化实例
Finally let’s apply this general discussion on optimization to the list of PLL configurations that we found in the above example.
最后，让我们讨论一下在上面的例子中如何优化锁相环的一系列配置。
Power
If low power consumption is the primary design concern we want to minimize VCO frequency and divide values.
Selecting N=3， Q=21， P=220 would be the best choice.
This operates the VCO at one of the lower frequencies， lower P and Q values， and has a reasonable PFD frequency.
功耗
如果低功耗是设计关注的重点，我们希望减小压控振荡器频率和分频器值。选择N = 3，Q = 21，P = 220将是最好的选择。这种设置可以使压控振荡器工作在更低的频率，更低的P和Q值，并有一个合理的PFD频率。
Startup / Settling Time
If startup / settling time is the primary concern， then from table 1 it is clear that the N=7， Q=9， P=220 is the most desirable.
It has an fPFD of more than two times any other configuration， resulting in a higher refresh rate on the loop filter voltage.
启动/设置时间
如果启动/设置时间是主要关注的，那么从表1中很明显可以看出，N = 7，Q = 9，P = 220是最理想的。它的fPFD 是任何其它的配置的2倍，从而在环路滤波器电压有较高的刷新频率。
Jitter
If low jitter is the primary concern， then N=7， Q=9， P=220 is again the most desirable.
It has an fPFD of more than two times any other configuration， resulting in a higher refresh rate on the loop filter voltage and the lowest jitter of all the possible configurations.
抖动
如果低抖动是首要关注的对象，那么N = 7，Q = 9，P = 220是最可取的。它的fPFD 是任何其它的配置的2倍，
从而在环路滤波器电压有较高的刷新频率，那么这是所有可能的配置方法中抖动最低的。
Phase Noise
Optimizing phase noise is highly application dependent and depends on specific reference oscillator and VCO noise performance.
The one design choice we can make based on our configuration list is to choose a high VCO frequency that is divided down.
N=7， Q=9， P=220 is probably the best because its PFD frequency is so much higher than N=8， Q=63， P=1760.
If the loop has high jitter， then the phase noise floor will rise significantly， swamping out any improvement the output divider is giving us.
相位噪声
优化相位噪声是高度依赖于应用的，它取决于特定参考振荡器和压控振荡器噪声性能。基于配置清单，我们可以做的是，选择较高的压控振荡器频率，降低分频值。N = 7，Q = 9，P = 220可能是最好的，因为它的PFD频率远高于N = 8，Q = 63，P = 1760情况下。如果环路有较高的抖动，那么相位噪声平面也将显著提高，这将覆没输出分配器给我们带来的任何改善。
Configuring a PLL for system applications can be an arduous task with lots of iteration.
By first solving for all frequency synthesis parameters that meet our needs， we can then make well founded design choices that maximize flexibility and minimize cost.
为系统应用配置一个锁相环可以是一个艰巨的任务，并且需要大量的反复工作。首先要解决所有的满足我们需求的频率合成技术参数
，我们才能作出良好的设计选择，才能最大幅度地提高灵活性并降低成本。
|
楼主
标题置顶
标题高亮
