''risc v 处理器的FPGA实现工程''这个好像出了一点问题
问题遇到的现象和发生背景问题相关代码，请勿粘贴截图运行结果及报错内容 Unspecified I/O Standard: 39 out of 60 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} . NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ck_io, led, btn_1, btn_2, btn_3, ck_miso, ck_mosi, ck_sck, ck_ss, led0_b, led0_g, led0_r, led1_b, led1_g, led1_r... and (the first 15 of 19 listed). Unconstrained Logical Port: 39 out of 60 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} . NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ck_io, led, btn_1, btn_2, btn_3, ck_miso, ck_mosi, ck_sck, ck_ss, led0_b, led0_g, led0_r, led1_b, led1_g, led1_r... and (the first 15 of 19 listed). Error(s) found during DRC. Bitgen not run.我的解答思路和尝试过的方法我想要达到的结果这代码就好好用代码框啊
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