2410eboot遇到问题求解
调试2410的wince遇到问题。下面的代码是eboot中打开mmu的代码,但是mmu打开后bl main就跳到了空的地址,之前到bl之前运行都是对的,小弟对于mmu不是太了解,有没有那位高手能帮我分析一下,不胜感激,最后付了OEMAddressTable<br />其中<br />PHYBASE EQU 0x30000000 ; physical start<br />PTs EQU 0x31E00000<br /><br />GWMMUINIT<br /> ; Compute physical address of the OEMAddressTable.<br />20 add r11, pc, #SDATA - (. + 8)<br /> ldr r10, =PTs ; (r10) = 1st level page table<br /><br /><br /> ; Setup 1st level page table (using section descriptor) <br /> ; Fill in first level page table entries to create "un-mapped" regions<br /> ; from the contents of the MemoryMap array.<br /> ;<br /> ; (r10) = 1st level page table<br /> ; (r11) = ptr to MemoryMap array<br /><br /> add r10, r10, #0x2000 ; (r10) = ptr to 1st PTE for "unmapped space"<br /> mov r0, #0x0E ; (r0) = PTE for 0: 1MB cachable bufferable<br /> orr r0, r0, #0x400 ; set kernel r/w permission<br />25 mov r1, r11 ; (r1) = ptr to MemoryMap array<br /><br /> <br />30 ldr r2, , #4 ; (r2) = virtual address to map Bank at<br /> ldr r3, , #4 ; (r3) = physical address to map from<br /> ldr r4, , #4 ; (r4) = num MB to map<br /><br /> cmp r4, #0 ; End of table?<br /> beq %f40<br /><br /> ldr r5, =0x1FF00000<br /> and r2, r2, r5 ; VA needs 512MB, 1MB aligned. <br /><br /> ldr r5, =0xFFF00000<br /> and r3, r3, r5 ; PA needs 4GB, 1MB aligned.<br /><br /> add r2, r10, r2, LSR #18<br /> add r0, r0, r3 ; (r0) = PTE for next physical page<br /><br />35 str r0, , #4<br /> add r0, r0, #0x00100000 ; (r0) = PTE for next physical page<br /> sub r4, r4, #1 ; Decrement number of MB left <br /> cmp r4, #0<br /> bne %b35 ; Map next MB<br /><br /> bic r0, r0, #0xF0000000 ; Clear Section Base Address Field<br /> bic r0, r0, #0x0FF00000 ; Clear Section Base Address Field<br /> b %b30 ; Get next element<br /> <br />40 tst r0, #8<br /> bic r0, r0, #0x0C ; clear cachable & bufferable bits in PTE<br /> add r10, r10, #0x0800 ; (r10) = ptr to 1st PTE for "unmapped uncached space"<br /> bne %b25 ; go setup PTEs for uncached space<br /> sub r10, r10, #0x3000 ; (r10) = restore address of 1st level page table<br /><br /> ; Setup mmu to map (VA == 0) to (PA == 0x30000000).<br /> ldr r0, =PTs ; PTE entry for VA = 0<br /> ldr r1, =0x3000040E ; uncache/unbuffer/rw, PA base == 0x30000000<br /> str r1, <br /><br /> ; uncached area.<br /> add r0, r0, #0x0800 ; PTE entry for VA = 0x0200.0000 , uncached <br /> ldr r1, =0x30000402 ; uncache/unbuffer/rw, base == 0x30000000<br /> str r1, <br /> <br /> ; Comment:<br /> ; The following loop is to direct map RAM VA == PA. i.e. <br /> ; VA == 0x30XXXXXX => PA == 0x30XXXXXX for S3C2400<br /> ; Fill in 8 entries to have a direct mapping for DRAM<br /> ;<br /> ldr r10, =PTs ; restore address of 1st level page table<br /> ldr r0, =PHYBASE<br /><br /> add r10, r10, #(0x3000 / 4) ; (r10) = ptr to 1st PTE for 0x30000000<br /><br /> add r0, r0, #0x1E ; 1MB cachable bufferable<br /> orr r0, r0, #0x400 ; set kernel r/w permission<br /> mov r1, #0 <br /> mov r3, #64<br />45 mov r2, r1 ; (r2) = virtual address to map Bank at<br /> cmp r2, #0x20000000:SHR:BANK_SHIFT<br /> add r2, r10, r2, LSL #BANK_SHIFT-18<br /> strlo r0, <br /> add r0, r0, #0x00100000 ; (r0) = PTE for next physical page<br /> subs r3, r3, #1<br /> add r1, r1, #1<br /> bgt %b45<br /><br /> ldr r10, =PTs ; (r10) = restore address of 1st level page table<br /><br /> ; The page tables and exception vectors are setup.<br /> ; Initialize the MMU and turn it on.<br /> mov r1, #1<br /> mcr p15, 0, r1, c3, c0, 0 ; setup access to domain 0<br /> mcr p15, 0, r10, c2, c0, 0<br /> mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs<br /> mov r1, #0x0071 ; Enable: MMU<br /> orr r1, r1, #0x0004 ; Enable the cache<br /><br /> ldr r0, =VirtualStart<br /><br /> cmp r0, #0 ; make sure no stall on "mov pc,r0" below<br /> mcr p15, 0, r1, c1, c0, 0<br /> mov pc, r0 ; & jump to new virtual address<br /> nop<br /><br /> ; MMU & caches now enabled.<br /> ; (r10) = physcial address of 1st level page table<br /> ;<br /><br />VirtualStart<br /><br /> mov sp, #0x8C000000<br /> add sp, sp, #0x30000 ; arbitrary initial super-page stack pointer<br /> <br /> ldr r0, = 0x91600054<br /> ldr r1, = 0x80 <br /> str r1, <br /><br /> bl Main<br /><br /><br /><br /> LTORG<br /><br />SDATA DATA<br /><br /> DCD 0x80000000, 0x02000000, 30 ; 30 MB SROM(SRAM/ROM) BANK 0<br /> DCD 0x82000000, 0x08000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 1<br /> DCD 0x84000000, 0x10000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 2<br /> DCD 0x86000000, 0x18000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 3<br /> DCD 0x88000000, 0x20000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 4<br /> DCD 0x8A000000, 0x28000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 5<br /> DCD 0x8C000000, 0x30000000, 64 ; 64 MB DRAM BANK 0,1<br /> DCD 0x90800000, 0x48000000, 1 ; Memory control register<br /> DCD 0x90900000, 0x49000000, 1 ; USB Host register<br /> DCD 0x90A00000, 0x4A000000, 1 ; Interrupt Control register<br /> DCD 0x90B00000, 0x4B000000, 1 ; DMA control register<br /> DCD 0x90C00000, 0x4C000000, 1 ; Clock & Power register<br /> DCD 0x90D00000, 0x4D000000, 1 ; LCD control register<br /> DCD 0x90E00000, 0x4E000000, 1 ; NAND flash control register<br /> DCD 0x91000000, 0x50000000, 1 ; UART control register<br /> DCD 0x91100000, 0x51000000, 1 ; PWM timer register<br /> DCD 0x91200000, 0x52000000, 1 ; USB device register<br /> DCD 0x91300000, 0x53000000, 1 ; Watchdog Timer register<br /> DCD 0x91400000, 0x54000000, 1 ; IIC control register<br /> DCD 0x91500000, 0x55000000, 1 ; IIS control register<br /> DCD 0x91600000, 0x56000000, 1 ; I/O Port register<br /> DCD 0x91700000, 0x57000000, 1 ; RTC control register<br /> DCD 0x91800000, 0x58000000, 1 ; A/D convert register<br /> DCD 0x91900000, 0x59000000, 1 ; SPI register<br /> DCD 0x91A00000, 0x5A000000, 1 ; SD Interface register<br /> DCD 0x92000000, 0x00000000, 2 ; 2 MB SROM(SRAM/ROM) BANK 0<br /> DCD 0x00000000, 0x00000000, 0 ; End of Table (MB MUST BE ZERO!)<br /> ALIGN<br />
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