求SI4438的驱动
本帖最后由 木头0 于 2015-5-8 21:24 编辑小弟最近在做msp430的相关课题，要用到无线收发功能，得用si4438，手上有一份SI4438的驱动，可实现无线模块的收发，但是小弟要用到SI4438的RSSI，可惜小弟才疏学浅，写不出获取SI4438的RSSI的函数。之前在网上找过一些函数，但读到的RSSI总是0。希望有大神能帮忙写个读取RSSI的函数，或者提供一份带读取RSSI的SI4438驱动。（驱动要是代码可见的） 本帖最后由 木头0 于 2015-5-8 22:14 编辑
RF接收函数
//RF接收函数
U8 rf_get_data(U8 * buf, U8 maxlen)
{
if ( radio_hal_NirqLevel() ) return 0;
/* Read ITs, clear pending ones */
si446x_get_int_status(0u, 0u, 0u);
/* check the reason for the IT */
if (Si446xCmd.GET_INT_STATUS.MODEM_PEND & SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_BIT)
{
/* Sync Word detected */
// Disabled in the project
}
if (Si446xCmd.GET_INT_STATUS.PH_PEND & SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_BIT)
{
/* CRC OK or not enabled */
/* Read the length of RX_FIFO */
si446x_fifo_info(0u);
maxlen = Si446xCmd.FIFO_INFO.RX_FIFO_COUNT < maxlen ?
Si446xCmd.FIFO_INFO.RX_FIFO_COUNT : maxlen ;
/* Packet RX */
si446x_read_rx_fifo(maxlen , buf);
/* clear the tx & rx fifo */
si446x_fifo_info(0x03);
return maxlen;
}
if (Si446xCmd.GET_INT_STATUS.PH_PEND & SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_BIT)
{
/* Reset tx & rx FIFO */
si446x_fifo_info( 0x03 );
}
return 0;
}
附上在网上找的读取rssi的代码，读取后总是0
//**************************************************************************************************************
// 名 称：unsigned int App_Read_Rssi_temp(void);
// 函数描述：读接收到的RSSI
// 输入参数：无
// 输出参数：是否读取成功，正确读取，就是读取成功，否则为读取不成功
// 注 意：
//**************************************************************************************************************
signed intApp_Read_Rssi_temp(void)
{
signed int temp;
si446x_get_modem_status(0x18);
temp = Si446xCmd.GET_MODEM_STATUS.CURR_RSSI;
return(temp);
} 我是这样读取RSSI的值,先用WDS软件设设置好在哪里读取RSSI的值。比如收到同步字之后，然后把这个RSSI的值放到快速寄存器A里面去，在然后在收到同步字的程序上面读取快速寄存器A的值就行了。 minton123 发表于 2015-5-11 14:13
我是这样读取RSSI的值,先用WDS软件设设置好在哪里读取RSSI的值。比如收到同步字之后，然后把这个RSSI的值放 ...
后来我发现我的寄存器配置文件没有对RSSI进行锁存，我就用WDS软件自己写了给配置文件，但是程序经常卡住接收程序里，等好久才能完成接收，而且RSSI测出来也很小（经过公式变换后），而且之后rssi就不变了。本人不是通信专业的，对通信和无线模块完全不懂，WDS软件的那些配置项，根本不知道什么意思。
并附上我之前用的驱动的配置文件（可以很好的收发，但没RSSI）
/*! @file radio_config.h
* @brief This file contains the automatically generated
* configurations.
*
* @n WDS GUI Version: 3.2.7.0
* @n Device: Si4438 Rev.: B1
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2014 Silicon Laboratories, Inc.
* @
*/
#ifndef RADIO_CONFIG_H_
#define RADIO_CONFIG_H_
// USER DEFINED PARAMETERS
// Define your own parameters here
// INPUT DATA
/*
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
// MOD_type: 3 Rsymb(sps): 45000 Fdev(Hz): 33750 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
// RF Freq.(MHz): 434.2 API_TC: 31 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
//
// # WB filter 1 (BW = 114.46 kHz);NB-filter 1 (BW = 114.46 kHz)//
// Modulation index: 1.5
*/
// CONFIGURATION PARAMETERS
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x02
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD {0xC5, 0xC5}
// CONFIGURATION COMMANDS
/*
// Command: RF_POWER_UP
// Description: Command to power-up the device and select the operational mode and functionality.
*/
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
/*
// Command: RF_GPIO_PIN_CFG
// Description: Configures the GPIO pins.
*/
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/*
// Set properties: RF_GLOBAL_XO_TUNE_1
// Number of properties: 1
// Group ID: 0x00
// Start ID: 0x00
// Default values: 0x40,
// Descriptions:
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
*/
#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
/*
// Set properties: RF_GLOBAL_CONFIG_1
// Number of properties: 1
// Group ID: 0x00
// Start ID: 0x03
// Default values: 0x20,
// Descriptions:
// GLOBAL_CONFIG - Global configuration settings.
*/
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
/*
// Set properties: RF_MODEM_MOD_TYPE_12
// Number of properties: 12
// Group ID: 0x20
// Start ID: 0x00
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
// Descriptions:
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
/*
// Set properties: RF_MODEM_FREQ_DEV_0_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x0C
// Default values: 0xD3,
// Descriptions:
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
/*
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
// Number of properties: 8
// Group ID: 0x20
// Start ID: 0x18
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
// Descriptions:
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
// MODEM_MDM_CTRL - MDM control.
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
*/
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10
/*
// Set properties: RF_MODEM_BCR_OSR_1_9
// Number of properties: 9
// Group ID: 0x20
// Start ID: 0x22
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
// Descriptions:
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
// MODEM_BCR_GEAR - RX BCR loop gear control.
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
*/
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0x4E, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0
/*
// Set properties: RF_MODEM_AFC_GEAR_7
// Number of properties: 7
// Group ID: 0x20
// Start ID: 0x2C
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
// Descriptions:
// MODEM_AFC_GEAR - RX AFC loop gear control.
// MODEM_AFC_WAIT - RX AFC loop wait time control.
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
*/
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x00, 0x12, 0x00, 0x23, 0x01, 0x5C, 0xA0
/*
// Set properties: RF_MODEM_AGC_CONTROL_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x35
// Default values: 0xE0,
// Descriptions:
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
*/
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
/*
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_3
// Number of properties: 3
// Group ID: 0x20
// Start ID: 0x38
// Default values: 0x11, 0x10, 0x10,
// Descriptions:
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
*/
#define RF_MODEM_AGC_WINDOW_SIZE_3 0x11, 0x20, 0x03, 0x38, 0x11, 0x11, 0x11
/*
// Set properties: RF_MODEM_OOK_PDTC_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x40
// Default values: 0x2B,
// Descriptions:
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
*/
#define RF_MODEM_OOK_PDTC_1 0x11, 0x20, 0x01, 0x40, 0x28 最后了
/*
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
// Number of properties: 12
// Group ID: 0x21
// Start ID: 0x18
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
// Descriptions:
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
/*
// Set properties: RF_PA_TC_1_1
// Number of properties: 1
// Group ID: 0x22
// Start ID: 0x03
// Default values: 0x5D,
// Descriptions:
// PA_TC - Configuration of PA ramping parameters.
*/
#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x3F
/*
// Set properties: RF_SYNTH_PFDCP_CPFF_7_1
// Number of properties: 7
// Group ID: 0x23
// Start ID: 0x00
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
// Descriptions:
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
*/
#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
/*
// Set properties: RF_MATCH_VALUE_1_12
// Number of properties: 12
// Group ID: 0x30
// Start ID: 0x00
// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// Descriptions:
// MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
// MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
// MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
// MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
// MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
// MATCH_CTRL_2 - Configuration of Match Byte 2.
// MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
// MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
// MATCH_CTRL_3 - Configuration of Match Byte 3.
// MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
// MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
// MATCH_CTRL_4 - Configuration of Match Byte 4.
*/
#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/*
// Set properties: RF_FREQ_CONTROL_INTE_8_1
// Number of properties: 8
// Group ID: 0x40
// Start ID: 0x00
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
// Descriptions:
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0F, 0x25, 0x8B, 0x44, 0x44, 0x20, 0xFE
// AUTOMATICALLY GENERATED CODE!
// DO NOT EDIT/MODIFY BELOW THIS LINE!
// --------------------------------------------
#ifndef FIRMWARE_LOAD_COMPILE
#define RADIO_CONFIGURATION_DATA_ARRAY { \
0x07, RF_POWER_UP, \
0x08, RF_GPIO_PIN_CFG, \
0x05, RF_GLOBAL_XO_TUNE_1, \
0x05, RF_GLOBAL_CONFIG_1, \
0x10, RF_MODEM_MOD_TYPE_12, \
0x05, RF_MODEM_FREQ_DEV_0_1, \
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
0x0D, RF_MODEM_BCR_OSR_1_9, \
0x0B, RF_MODEM_AFC_GEAR_7, \
0x05, RF_MODEM_AGC_CONTROL_1, \
0x07, RF_MODEM_AGC_WINDOW_SIZE_3, \
0x05, RF_MODEM_OOK_PDTC_1, \
0x0C, RF_MODEM_OOK_CNT1_8, \
0x05, RF_MODEM_RSSI_COMP_1, \
0x05, RF_MODEM_CLKGEN_BAND_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
0x05, RF_PA_TC_1, \
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
0x0C, RF_FREQ_CONTROL_INTE_8, \
0x08, RF_START_RX, \
0x05, RF_GLOBAL_CLK_CFG_1, \
0x05, RF_GLOBAL_CONFIG_1_1, \
0x08, RF_INT_CTL_ENABLE_4, \
0x08, RF_FRR_CTL_A_MODE_4, \
0x0D, RF_PREAMBLE_TX_LENGTH_9, \
0x09, RF_SYNC_CONFIG_5, \
0x05, RF_PKT_CRC_CONFIG_1, \
0x08, RF_PKT_WHT_SEED_15_8_4, \
0x10, RF_PKT_LEN_12, \
0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \
0x10, RF_PKT_FIELD_5_CRC_CONFIG_12, \
0x0D, RF_PKT_RX_FIELD_3_CRC_CONFIG_9, \
0x10, RF_MODEM_MOD_TYPE_12_1, \
0x05, RF_MODEM_FREQ_DEV_0_1_1, \
0x0C, RF_MODEM_TX_RAMP_DELAY_8_1, \
0x0D, RF_MODEM_BCR_OSR_1_9_1, \
0x0B, RF_MODEM_AFC_GEAR_7_1, \
0x05, RF_MODEM_AGC_CONTROL_1_1, \
0x07, RF_MODEM_AGC_WINDOW_SIZE_3_1, \
0x05, RF_MODEM_OOK_PDTC_1_1, \
0x0D, RF_MODEM_OOK_CNT1_9, \
0x05, RF_MODEM_RSSI_CONTROL_1, \
0x05, RF_MODEM_RSSI_COMP_1_1, \
0x05, RF_MODEM_CLKGEN_BAND_1_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
0x05, RF_PA_TC_1_1, \
0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
0x10, RF_MATCH_VALUE_1_12, \
0x0C, RF_FREQ_CONTROL_INTE_8_1, \
0x00 \
}
#else
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
#endif
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT {0x42, 0x55, 0x54, 0x54, 0x4F, 0x4E, 0x31} // BUTTON1
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH {}
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
#error "This property must be defined!"
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESETRADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD
#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT
#endif
#define RADIO_CONFIGURATION_DATA { \
Radio_Configuration_Data_Array, \
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET, \
RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD \
}
#endif /* RADIO_CONFIG_H_ */ minton123 发表于 2015-5-11 14:13
我是这样读取RSSI的值,先用WDS软件设设置好在哪里读取RSSI的值。比如收到同步字之后，然后把这个RSSI的值放 ...
刚刚测试了一下，并不是卡在接收程序里，而是被判断为接收不成功。所以丢包率很高。 木头0 发表于 2015-5-11 21:33
刚刚测试了一下，并不是卡在接收程序里，而是被判断为接收不成功。所以丢包率很高。 ...
哪你这个SI4438的电路有没有电子开关的，就是有接收和发送用SI4438的GPIO口来回切换的，如果有，就要配置相应的存寄器。还有就是接收的跟发送的各种参数是否是相对应。可以开前导码中断，以及同步字中断来看接收否正常的。SI4438有B版本还有C版本的。会有不一样的配置的。看你上面用WDS生成的是B版的。通信的频点是否是一样的。SI4438的晶振是否30M。 minton123 发表于 2015-5-12 09:48
哪你这个SI4438的电路有没有电子开关的，就是有接收和发送用SI4438的GPIO口来回切换的，如果有，就要配置 ...
谢谢你的建议，后来我经过各种尝试后发现是WDS设置中，数据包设置与我所驱动不同，在数据包格式中使能数据包长度选项后，就可以正常收发了。 由于我用的是一家公司的内部资料，不方便进行分享，现在附上我在网上找的一个si4438的驱动，和我所用驱动有很多相似之处。由于我没对这个确定进行测试，无法保证它的可行性。这个驱动的好处是用户可见，而且有很多注释，我当时写程序，很大程度上参考了它。
注：本驱动非我所写，是我在PUDN上下的，版权归原作者所有。由于时间已久，无法找到原作者信息，在此表示抱歉。
minton123 发表于 2015-5-12 09:48
哪你这个SI4438的电路有没有电子开关的，就是有接收和发送用SI4438的GPIO口来回切换的，如果有，就要配置 ...
我现在用芯片印着“44381C”是B版还是C版，好晕啊 您好！我想问下怎样判断4438发送数据是否成功呢？ 求问楼主关于SI4438的CCA功能是如何设置的。 楼主好人，资料好详细，多谢了 木头0 发表于 2015-5-13 20:58
由于我用的是一家公司的内部资料，不方便进行分享，现在附上我在网上找的一个si4438的驱动，和我所用驱 ...
能把你的配置文件发一分吗 大哥能给个QQ联系方式吗有很多问题想请教你 hanson_chc 发表于 2015-9-22 20:46
能把你的配置文件发一分吗
:) 木头0 发表于 2015-5-13 20:58
由于我用的是一家公司的内部资料，不方便进行分享，现在附上我在网上找的一个si4438的驱动，和我所用驱 ...
你有没有关于SI4438无线收发芯片的一些资料啊，能不能发我点 我是刚接触无线通信这块什么都不懂 能不能发些基础的资料给我 谢啦:lol 非常感谢这个可以参考一下 最近在做这个 minton123 发表于 2015-5-11 14:13
我是这样读取RSSI的值,先用WDS软件设设置好在哪里读取RSSI的值。比如收到同步字之后，然后把这个RSSI的值放 ...
你好，我现在在调试SI4438，可以实现收发数据，按照你的办法，在WDS中设置RSSI所存在同步码之后，在收到同步码后， 通过快速寄存器A读取RSSI，获取的值一直是0。
下面是我的WDS配置及读取RSSI的程序，麻烦帮我判断是哪里出的问题，多谢！
接收数据程序：
u8 bRadio_Check_Tx_RX(void)
{
u8 kk;
u8 tmp;
u8 rssi = 0;
if(radio_hal_NirqLevel() == RESET)
{
/* Read ITs, clear pending ones */
si446x_get_int_status(0u, 0u, 0u);
kk = Si446xCmd.GET_INT_STATUS.CHIP_PEND;
if(kk & SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_BIT)
{
/* State change to */
si446x_change_state(SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_SLEEP);
/* Reset FIFO */
si446x_fifo_info(SI446X_CMD_FIFO_INFO_ARG_RX_BIT);
/* State change to */
si446x_change_state(SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_RX);
}
/* check the reason for the IT */
if(Si446xCmd.GET_INT_STATUS.MODEM_PEND & SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_BIT)
{//同步码检测
si446x_frr_a_read(rssi);//读取快速寄存器A中存储的RSSI
while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET);
USART_SendData(USART1,rssi);//串口打印输出
GPIO_Reverse(RECEIVEUART_LED_PORT, RECEIVEUART_LED_PIN);
}
if(Si446xCmd.GET_INT_STATUS.PH_PEND & SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_BIT)
{
/* Read the length of RX_FIFO */
si446x_fifo_info(0u);
/* Packet RX */
//si446x_read_rx_fifo(Si446xCmd.FIFO_INFO.RX_FIFO_COUNT, &fixRadioPacket);
si446x_read_rx_fifo(Si446xCmd.FIFO_INFO.RX_FIFO_COUNT, variableRadioPacket);
UART1ToPC(variableRadioPacket,Si446xCmd.FIFO_INFO.RX_FIFO_COUNT);
return TRUE;
}
if (Si446xCmd.GET_INT_STATUS.PH_PEND & SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_BIT)
{
/* Reset FIFO */
si446x_fifo_info(SI446X_CMD_FIFO_INFO_ARG_RX_BIT);
}
}
return 0;
}
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