GFD3F330 DMA奇怪问题

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 楼主 | 2019-1-5 15:47 | 显示全部楼层 |阅读模式
今天试着通过TIMER1+DMA5向GPIO口传送512个数据,DMA开放了TC,HT 2个中断(传送半中断和传送完成中断),应在传送了256数据和512个数据时产生DMA中断,但实际上是在传送了249和507时就产生了中断。程序如下,望大侠指点
void TIMER1_Configuration(void)
{
        /* TIMER1 DMA Transfer example -------------------------------------------------
    TIMER1CLK = 72MHz, Prescaler = 72
    TIMER1 counter clock = SystemCoreClock/72 = 1MHz.

    The objective is to configure TIMER1 channel 1 to generate PWM
    signal with a frequency equal to 1KHz and a variable duty cycle(25%,50%,75%) that is
    changed by the DMA after a specific number of Update DMA request.

    The number of this repetitive requests is defined by the TIMER1 Repetition counter,
    each 2 Update Requests, the TIMER1 Channel 1 Duty Cycle changes to the next new
    value defined by the buffer .
    -----------------------------------------------------------------------------*/
    TIMER_BaseInitPara TIMER_TimeBaseStructure;
    TIMER_OCInitPara  TIMER_OCInitStructure;
        DMA_InitPara DMA_InitStructure;
        NVIC_InitPara NVIC_InitStructure;
    /* TIMERS clock enable */
    RCC_APB2PeriphClock_Enable(RCC_APB2PERIPH_TIMER1,ENABLE);
    //RCC_APB1PeriphClock_Enable(RCC_APB1PERIPH_TIMER2|RCC_APB1PERIPH_TIMER3|RCC_APB1PERIPH_TIMER6|RCC_APB1PERIPH_TIMER14,ENABLE);

    /* TIMER1  configuration */
    TIMER_DeInit(TIMER1);
    TIMER_TimeBaseStructure.TIMER_Prescaler         = 0;                                    //ÉèÖÃÔ¤·ÖƵ
    TIMER_TimeBaseStructure.TIMER_Period            = Fre;
    TIMER_TimeBaseStructure.TIMER_ClockDivision     = 0;                //ÉèÖÃʱÖÓ·ÖƵϵÊý£º²»·ÖƵ
        //TIMER_TimeBaseStructure.TIMER_Pulse = 3;
        TIMER_TimeBaseStructure.TIMER_CounterMode       = TIMER_COUNTER_UP;
    //TIMER_TimeBaseStructure.TIMER_RepetitionCounter = 1;
    TIMER_BaseInit(TIMER1,&TIMER_TimeBaseStructure);

    /* CH1 Configuration in PWM mode */
    TIMER_OCInitStructure.TIMER_OCMode       = TIMER_OC_MODE_PWM1;
    TIMER_OCInitStructure.TIMER_OCPolarity   = TIMER_OC_POLARITY_HIGH;
    TIMER_OCInitStructure.TIMER_OCNPolarity  = TIMER_OCN_POLARITY_HIGH;
    TIMER_OCInitStructure.TIMER_OutputState  = TIMER_OUTPUT_STATE_ENABLE;
    TIMER_OCInitStructure.TIMER_OutputNState = TIMER_OUTPUTN_STATE_ENABLE;
    TIMER_OCInitStructure.TIMER_OCIdleState  = TIMER_OC_IDLE_STATE_SET;
    TIMER_OCInitStructure.TIMER_OCNIdleState = TIMER_OCN_IDLE_STATE_RESET;
     
//   TIMER_OCInitStructure.TIMER_Pulse = FreDa[0];
//   TIMER_OC3_Init(TIMER1, &TIMER_OCInitStructure);
//   TIMER_OC3_Preload(TIMER1,TIMER_OC_PRELOAD_DISABLE);

    /* TIMER1 output enable */
//   TIMER_CtrlPWMOutputs(TIMER1,ENABLE);
    /* Auto-reload preload enable */
//   TIMER_CARLPreloadConfig(TIMER1,ENABLE);
    /* TIMER1 Update DMA Request enable */
    TIMER_DMACmd( TIMER1, TIMER_DMA_UPDATE, ENABLE);
    /* TIMER enable counter*/
    TIMER_Enable( TIMER1, DISABLE );
       


    /* DMA1 clock enable */
    RCC_AHBPeriphClock_Enable(RCC_AHBPERIPH_DMA1,ENABLE);

    /* DMA1 Channel5 Config */
    DMA_DeInit(DMA1_CHANNEL5);
    //DMA_InitStructure.DMA_PeripheralBaseAddr = TIMER3_CHCC1;
        DMA_InitStructure.DMA_PeripheralBaseAddr = GPIOA_ODR ;
    DMA_InitStructure.DMA_MemoryBaseAddr     = (uint32_t)&DDS_Buf;//buf;
    DMA_InitStructure.DMA_DIR                = DMA_DIR_PERIPHERALDST;
    DMA_InitStructure.DMA_BufferSize         = 512;
    DMA_InitStructure.DMA_PeripheralInc      = DMA_PERIPHERALINC_DISABLE;//ÍâÉèµØÖ·¹Ì¶¨
    DMA_InitStructure.DMA_MemoryInc          = DMA_MEMORYINC_ENABLE;//ÄÚ´æµØÖ·¹Ì¶¨
    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PERIPHERALDATASIZE_HALFWORD;//ÍâÉèÊý¾Ý¿í¶ÈΪ16λ
    DMA_InitStructure.DMA_MemoryDataSize     = DMA_MEMORYDATASIZE_HALFWORD;//»º´æÊý¾Ý¿í¶È
    DMA_InitStructure.DMA_Mode               = DMA_MODE_CIRCULAR;//Ñ­»·´«Êä
    DMA_InitStructure.DMA_Priority           = DMA_PRIORITY_HIGH;//ÓÅÏȼ¶
    DMA_InitStructure.DMA_MTOM               = DMA_MEMTOMEM_DISABLE;//δÉè³ÉÄÚ´æµ½ÄÚ´æģʽ
    DMA_Init(DMA1_CHANNEL5, &DMA_InitStructure);
   
       
        /* Enable the USARTx Interrupt */
    NVIC_InitStructure.NVIC_IRQ = DMA1_Channel4_5_IRQn;//ÖжÏͨµÀ
    NVIC_InitStructure.NVIC_IRQPreemptPriority = 0;//ÇÀÕ¼ÓÅÏȼ¶
    NVIC_InitStructure.NVIC_IRQSubPriority = 0;//¸±ÓÅÏȼ¶
    NVIC_InitStructure.NVIC_IRQEnable = ENABLE;//Ñ¡ÔñµÄͨµÀʹÄÜ
    NVIC_Init(&NVIC_InitStructure);

    DMA_INTConfig(DMA1_CHANNEL5, DMA_INT_TC|DMA_INT_HT, ENABLE);
   
       
    /* DMA1 Channel5 enable */
    DMA_Enable(DMA1_CHANNEL5, ENABLE);
}

/**
  * @brief  This function handles DMA1_Channel4_5 Handler.
  * @param  None
  * @retval None  DMA1_INT_TC5
  */
void DMA1_Channel4_5_IRQHandler(void)
{
        uint16_t size;
        if((DMA_GetIntBitState(DMA1_INT_TC5)!= RESET)||(DMA_GetIntBitState(DMA1_INT_HT5)!= RESET))
    {     
                size = DMA_GetCurrDataCounter(DMA1_CHANNEL5);
                if((size==256)||(size==512))
                {       
                        DDS_(size);
                        DMA_ClearIntBitState(DMA1_INT_TC5|DMA1_INT_HT5);
                }
                else
                {
                        //DMA_ClearIntBitState(DMA1_INT_GL5|DMA1_INT_ERR5);
                }
                DMA_ClearIntBitState(DMA1_INT_GL5);
                DMA_ClearIntBitState(DMA_INT_TC|DMA_INT_HT);
        }
        //DMA_ClearIntBitState(DMA1_INT_GL5|DMA1_INT_ERR5);
}
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