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我做的一个自动门，源程序如下：library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br />entity zdm is<br />port (<br />clk: in std_logic;<br />sen_1,sen_2 : in std_logic;<br />device_open : out std_logic;<br />device_close:out std_logic ;<br />close_min:in std_logic;<br />open_max: in std_logic);<br />end zdm;<br />architecture beh of zdm is<br />type state_type is (qa,qb,qc,qd);<br />signal state: state_type;<br />begin<br />process (clk,open_max,close_min)<br />begin<br />if clk'event and clk = '1' then<br />case state is<br />when qa =>device_open<='0';<br />device_close<='0';<br />if (sen_2 or sen_1)<='1' then<br />state<=qb;<br />else state<=qa;<br />end if;<br />when qb =>device_open<='1';<br />device_close<='0';<br />if (sen_2 or sen_1)<='1' then<br />if open_max<='1' then<br />state<=qd;<br />else state<=qa;<br />end if;<br />else state<=qc;<br />end if ;<br />when qc =>device_open<='0';<br />device_close<='1';<br />if (sen_1 or sen_2)<='0' then<br />if close_min<='1'then<br />state <=qa;<br />end if;<br />else state<=qb;<br />end if ;<br />when qd=>device_open<='0';<br />device_close<='0';<br />if (sen_1 or sen_2)<='0'then<br />state<=qc;<br />else state<=qd;<br />end if;<br />when others=>state<=qa;<br />end case;<br />end process;<br />end beh;<br />我在quartus2上编译成功，但是防真波形不符，原版程序是书上下的，因为原版程序在qusrtus2上编译有错，但是在ＭＡＸ＋plus上成功，我只学了quartus所以我做了一点改动，把１9行成if clk'event and clk = '1' then，原版程序１9行为wait until clk'event and clk = '1' 后编译成功，但是防真波形不符合逻辑，状态图，qc,qb,在不停的自转，问题在哪呢？Sen_1 和sen_2 为传感器信号，为高电<br />平时有人活动；Clock 为0.1s 时钟脉冲输<br />入；o p e n _ m a x 开门最大控制点，当<br />o p e n _ m a x 为高电平时，为开最大。<br />Close_min关门最小控制点，当close_min为<br />高电平时，为关最小。Device_open 为高电<br />平时，执行开门驱动。Device_close为高电<br />平时为，执行关门驱动。应用状态机设计，<br />Ｑ A 为关门停止状态，QB 为开门状态，QC<br />为关门状态，Q D 为开最大停止状态。<br /> |
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