日志
一个轻量级的Viterbi解码器
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A light-weighted Viterbi Decoder implemented by FPGA
Beijing Institute of Technology,
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Abstract—In this paper, a light-weighted pipelined serial Viterbi Decoder
is implemented for resource saving purpose. The traceback module of the
decoder consumes fewer logical resources by employing a RAM-based
Register Exchange architecture. All the metric and traceback bits are stored in
the RAM to save logical resources. Synthesis results show that, the proposed
architecture can save more than half of resource utilization than fabric IP core
and has the minimum logic consumption than almost other schemes we can
find with nearly no performance loss.
正文http://UploadFiles/2012-4/292010265752.rar
我的第一篇paper，提供了一个最为精简的Viterbi实现，基本已经达到了业界的设计极限。
可以提供Xilinx 和Altera的代码，为了节省空间，本链接仅提供Xilinx 的 Modelsim
源代码 UploadFiles/2012-4/29205920071.rar
