功能：初始化LPC2142内部寄存器，包括设置PLL、初始化中断向量、设置代码加密等。由Keil的模板改来的，要与我的makefile和lpc2142-ROM.ld配合使用。

/***********************************************************************/
/*  This file is part of the uVision/ARM development tools             */
/*  Copyright KEIL ELEKTRONIK GmbH 2002-2005                           */
/***********************************************************************/
/*                                                                     */
/*  STARTUP.S:  Startup file for Philips LPC213x/LPC214x device series */
/*                                                                     */
/***********************************************************************
 *  The STARTUP.S code is executed after CPU Reset. This file may be
 *  translated with the following SET symbols. In uVision these SET
 *  symbols are entered under Options - ASM - Set.
 *
 *  REMAP: when set the startup code initializes the register MEMMAP
 *  which overwrites the settings of the CPU configuration pins. The
 *  startup and interrupt vectors are remapped from:
 *     0x00000000  default setting (not remapped)
 *     0x80000000  when EXTMEM_MODE is used
 *     0x40000000  when RAM_MODE is used
 *
 *  EXTMEM_MODE: when set the device is configured for code execution
 *  from external memory starting at address 0x80000000. The startup
 *  vectors are located to 0x80000000.
 *
 *  RAM_MODE: when set the device is configured for code execution
 *  from on-chip RAM starting at address 0x40000000. The startup
 *  vectors are located to 0x40000000.
 ************************************************************************/
 .extern main
 .text
 .code 32

 .align  0

 .extern __bss_beg__
 .extern __bss_end__
 .extern __stack_end__
 .extern __data_beg__
 .extern __data_end__
 .extern __data+beg_src__

 .global start
 .global endless_loop

 /* Stack Sizes */
    .set  UND_STACK_SIZE, 0x00000004
    .set  ABT_STACK_SIZE, 0x00000004
    .set  FIQ_STACK_SIZE, 0x00000004
    .set  IRQ_STACK_SIZE, 0X00000400
    .set  SVC_STACK_SIZE, 0x00000400

 /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
    .set  MODE_USR, 0x10            /* User Mode */
    .set  MODE_FIQ, 0x11            /* FIQ Mode */
    .set  MODE_IRQ, 0x12            /* IRQ Mode */
    .set  MODE_SVC, 0x13            /* Supervisor Mode */
    .set  MODE_ABT, 0x17            /* Abort Mode */
    .set  MODE_UND, 0x1B            /* Undefined Mode */
    .set  MODE_SYS, 0x1F            /* System Mode */

    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */

/* VPBDIV definitions*/
  .equ  VPBDIV,   0xE01FC100
  .set  VPBDIV_VALUE, 0x00000000
  
/* Phase Locked Loop (PLL) definitions*/  
  .equ  PLL_BASE,  0xE01FC080
  .equ  PLLCON_OFS,  0x00
  .equ  PLLCFG_OFS,  0x04
  .equ  PLLSTAT_OFS,  0x08
  .equ  PLLFEED_OFS,  0x0C
  
        .equ PLLCON_PLLE,   (1<<0)      /* PLL Enable */
        .equ PLLCON_PLLC,   (1<<1)      /* PLL Connect */
        .equ PLLSTAT_LOCK,  (1<<10)     /* PLL Lock Status */ 
  .equ PLLCFG_MSEL,   ((PLL_MUL - 1) << 0)
  .equ PLLCFG_PSEL, (0x02 << 5)
  .equ PLLCFG_Val, (PLLCFG_MSEL|PLLCFG_PSEL)
  
   
  .equ  MEMMAP,  0xE01FC040     /*Memory Mapping Control*/
  
  
/* Memory Accelerator Module (MAM) definitions*/

  .equ  MAM_BASE,  0xE01FC000
  .equ  MAMCR_OFS,  0x00
  .equ  MAMTIM_OFS,  0x04
        .equ  MAMCR_Val,    0x00000002
        .equ  MAMTIM_Val,   0x00000004
  
  .equ  VICIntEnClr, 0xFFFFF014
  .equ  VICIntSelect, 0xFFFFF00C

/* Setup the operating mode & stack.*/
/* --------------------------------- */
        .global _start, start, _reset, reset,
        .func   _start,

_start:
start:
_reset:
reset:

/* Setup PLL */
#if (PLL_MUL>1)

  ldr     r0, =PLL_BASE
  mov  r1, #0xAA
  mov  r2, #0x55

/* Configure and Enable PLL */
  mov     r3, #PLLCFG_Val
  str     r3, [r0, #PLLCFG_OFS]
  mov     r3, #PLLCON_PLLE
  str     r3, [r0, #PLLCON_OFS]
  str     r1, [r0, #PLLFEED_OFS]
  str     r2, [r0, #PLLFEED_OFS]

/*  Wait until PLL Locked */
7:  ldr     r3, [r0, #PLLSTAT_OFS]
  ands    r3, r3, #PLLSTAT_LOCK
  beq     7b

/*  Switch to PLL Clock */
  mov     r3, #(PLLCON_PLLE|PLLCON_PLLC)
  str     r3, [r0, #PLLCON_OFS]
  str     r1, [r0, #PLLFEED_OFS]
  str     R2, [r0, #PLLFEED_OFS]
  
#endif /*PLL_SETUP*/

#if (REMAP)
  mov     r0, =MEMMAP
#if (EXTMEM_MODE)               
        mov     r1, #3
#elseif (RAM_MODE)               
        mov     r1, #2
#else
        mov     r1, #1
#endif               
        str     r1, [r0]
#endif

/* Setup MAM */
  ldr  r0, =MAM_BASE
  mov  r1, #MAMTIM_Val
  str  r1, [r0, #MAMTIM_OFS]
  mov  r1, #MAMCR_Val
  str  r1, [r0, #MAMCR_OFS]

/* Setup VPBDIV */
  ldr  r0, =VPBDIV
  ldr     r1, =VPBDIV_VALUE
  str  r1, [r0]
  
/* Memory Mapping */
  ldr     r0, =MEMMAP
#if defined(RUN_FROM_RAM)
  mov  r1, #2
#else
  mov  r1, #1
#endif
  str  r1, [r0]
  
  /* clear all interrupts */
  ldr     r0, =VICIntEnClr
  mov  r1, #0xFFFFFFFF
  str  r1, [r0]
  ldr     r0, =VICIntSelect
  mov  r1, #0x00000000
  str  r1, [r0] 
 
 /* Setup a stack for each mode - note that this only sets up a usable stack
 for system/user, SWI and IRQ modes.   Also each mode is setup with
 interrupts initially disabled. */
    ldr   r0, .LC6
    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode
    mov   sp, r0
    sub   r0, r0, #UND_STACK_SIZE
    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
    mov   sp, r0
    sub   r0, r0, #ABT_STACK_SIZE
    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
    mov   sp, r0
    sub   r0, r0, #FIQ_STACK_SIZE
    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
    mov   sp, r0
    sub   r0, r0, #IRQ_STACK_SIZE
    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
    mov   sp, r0
    sub   r0, r0, #SVC_STACK_SIZE
    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
    mov   sp, r0

 /* We want to start in supervisor mode.  Operation will switch to system
 mode when the first task starts. */
 msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT

 /* Clear BSS. */

 mov     a2, #0   /* Fill value */
 mov  fp, a2   /* Null frame pointer */
 mov  r7, a2   /* Null frame pointer for Thumb */

 ldr  r1, .LC1  /* Start of memory block */
 ldr  r3, .LC2  /* End of memory block */
 subs r3, r3, r1      /* Length of block */
 beq  .end_clear_loop
 mov  r2, #0

.clear_loop:
 strb r2, [r1], #1
 subs r3, r3, #1
 bgt  .clear_loop

.end_clear_loop:

 /* Initialise data. */

 ldr  r1, .LC3  /* Start of memory block */
 ldr  r2, .LC4  /* End of memory block */
 ldr  r3, .LC5
 subs r3, r3, r1  /* Length of block */
 beq  .end_set_loop

.set_loop:
 ldrb r4, [r2], #1
 strb r4, [r1], #1
 subs r3, r3, #1
 bgt  .set_loop

.end_set_loop:
 
 mov  r0, #0          /* no arguments  */
 mov  r1, #0          /* no argv either */

 bl  main

endless_loop:
 b               endless_loop

 .align 0

 .LC1:
 .word   __bss_beg__
 .LC2:
 .word   __bss_end__
 .LC3:
 .word   __data_beg__
 .LC4:
 .word   __data_beg_src__
 .LC5:
 .word   __data_end__
 .LC6:
 .word   __stack_end__

 /* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
 a null loop. */

.section .startup,"ax"
         .code 32
         .align 0

 b     _start      /* reset - _start   */
 ldr   pc, _undf      /* undefined - _undf  */
 ldr   pc, _swi      /* SWI - _swi    */
 ldr   pc, _pabt      /* program abort - _pabt */
 ldr   pc, _dabt      /* data abort - _dabt  */
 nop         /* reserved     */
 ldr   pc, [pc,#-0xFF0]    /* IRQ - read the VIC  */
 ldr   pc, _fiq      /* FIQ - _fiq    */

_undf:  .word __undf                    /* undefined    */
_swi:   .word vPortYieldProcessor       /* SWI      */
_pabt:  .word __pabt                    /* program abort   */
_dabt:  .word __dabt                    /* data abort    */
_fiq:   .word __fiq                     /* FIQ      */
 
__undf: b     .                         /* undefined    */
__pabt: b     .                         /* program abort   */
__dabt: b     .                         /* data abort    */
__fiq:  b     .           /* FIQ      */
                      
#if defined(CODE_PROTECTION)
.org 0x01FC
.word 0x87654321
#endif