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// MSP430x42x0 Demo - FLL+, Runs Internal DCO at 2.45MHz
|
//******************************************************************************
// MSP430x42x0 Demo - FLL+, Runs Internal DCO at 2.45MHz
//
// Description: This program demonstrates setting the internal DCO to run at
// 2.45MHz with auto-calibration by the FLL+ circuitry.
// ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = (74+1) x ACLK = 2457600Hz
// //* An external watch crystal between XIN & XOUT is required for ACLK *//
//
// MSP430F4270
// -----------------
// /|\| XIN|-
// | | | 32kHz
// --|RST XOUT|-
// | |
// | P1.1/MCLK|--> MCLK = 2.45Mhz
// | |
// | P1.5/ACLK|--> ACLK = 32kHz
// | |
//
// L. Westlund / S. Karthikeyan
// Texas Instruments Inc.
// June 2005
// Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.30A
//*****************************************************************************
#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
SCFI0 |= FN_2; // Set DCO operating range
FLL_CTL0 |= XCAP14PF; // Set load capacitance for xtal
SCFQCTL = 74; // (74+1) x 32768 = 2.45Mhz
P1DIR = 0x22; // P1.1,5 to output direction
P1SEL = 0x22; // P1.1,5 to output MCLK & ACLK
while(1); // Loop in place
}
