HotCRC CRC32R_EDB88320_FFFFFFFF_00000000 FPGA模块 HotPower@163.com（菜农独创）

复制

/*-----------------------------------------------------------------------------------------------

      HotCRC CRC32R_EDB88320_FFFFFFFF_00000000 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 12:04:42

-----------------------------------------------------------------------------------------------*/

module CRC32R_EDB88320(clk, rst, data, outcrc32)

input clk, rst;

input [7:0] data;

output reg[31:0] outcrc32;

reg [31:0] crc32;



task CRC32R_EDB88320;

inout[31:0] crc32;

input[7:0] indata;

    crc32 = crc32[31:8] ^ CRC32R_EDB88320_Table(crc32[7:0] ^ indata);

endtask



function [31:0] CRC32R_EDB88320_Table;

    input [7:0] data;

    CRC32R_EDB88320_Table = CRC32R_EDB88320_Table0(data[1:0]) ^ CRC32R_EDB88320_Table1(data[3:2]) ^ CRC32R_EDB88320_Table2(data[5:4]) ^ CRC32R_EDB88320_Table3(data[7:6]);

endfunction



function [31:0] CRC32R_EDB88320_Table0;

    input[1:0] data;

    case(data)

        2'b00: CRC32R_EDB88320_Table0 = 32'h00000000; 2'b01: CRC32R_EDB88320_Table0 = 32'h77073096; 2'b10: CRC32R_EDB88320_Table0 = 32'hEE0E612C; 2'b11: CRC32R_EDB88320_Table0 = 32'h990951BA;

        default: CRC32R_EDB88320_Table0 = 32'h0000_0000;

    endcase

endfunction



function [31:0] CRC32R_EDB88320_Table1;

    input[1:0] data;

    case(data)

        2'b00: CRC32R_EDB88320_Table1 = 32'h00000000; 2'b01: CRC32R_EDB88320_Table1 = 32'h076DC419; 2'b10: CRC32R_EDB88320_Table1 = 32'h0EDB8832; 2'b11: CRC32R_EDB88320_Table1 = 32'h09B64C2B;

        default: CRC32R_EDB88320_Table1 = 32'h0000_0000;

    endcase

endfunction



function [31:0] CRC32R_EDB88320_Table2;

    input[1:0] data;

    case(data)

        2'b00: CRC32R_EDB88320_Table2 = 32'h00000000; 2'b01: CRC32R_EDB88320_Table2 = 32'h1DB71064; 2'b10: CRC32R_EDB88320_Table2 = 32'h3B6E20C8; 2'b11: CRC32R_EDB88320_Table2 = 32'h26D930AC;

        default: CRC32R_EDB88320_Table2 = 32'h0000_0000;

    endcase

endfunction



function [31:0] CRC32R_EDB88320_Table3;

    input[1:0] data;

    case(data)

        2'b00: CRC32R_EDB88320_Table3 = 32'h00000000; 2'b01: CRC32R_EDB88320_Table3 = 32'h76DC4190; 2'b10: CRC32R_EDB88320_Table3 = 32'hEDB88320; 2'b11: CRC32R_EDB88320_Table3 = 32'h9B64C2B0;

        default: CRC32R_EDB88320_Table3 = 32'h0000_0000;

    endcase

endfunction





always [url=home.php?mod=space&uid=72445]@[/url] (posedge clk or negedge rst)

begin

    if (!rst)

    begin

        crc32 <= 32'hFFFFFFFF;

    end

    else

    begin

        CRC32R_EDB88320(crc32, data);

        outcrc32 <= crc32;

        crc32 <= crc32;

    end

end

endmodule