HotCRC CRC64L_42F0E1EBA9EA3693_FFFFFFFFFFFFFFFF_0000000000000000 FPGA模块 HotPower@163.com（菜农独创）

复制

/*-----------------------------------------------------------------------------------------------

      HotCRC CRC64L_42F0E1EBA9EA3693_FFFFFFFFFFFFFFFF_0000000000000000 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 12:17:07

-----------------------------------------------------------------------------------------------*/

module CRC64L_42F0E1EBA9EA3693(clk, rst, data, outcrc64)

input clk, rst;

input [7:0] data;

output reg[63:0] outcrc64;

reg [63:0] crc64;



task CRC64L_42F0E1EBA9EA3693;

inout[63:0] crc64;

input[7:0] indata;

    crc64 = {crc64[55:0], 8'h00} ^ CRC64L_42F0E1EBA9EA3693_Table(crc64[63:56] ^ indata);

endtask



function [63:0] CRC64L_42F0E1EBA9EA3693_Table;

    input [7:0] data;

    CRC64L_42F0E1EBA9EA3693_Table = CRC64L_42F0E1EBA9EA3693_Table0(data[1:0]) ^ CRC64L_42F0E1EBA9EA3693_Table1(data[3:2]) ^ CRC64L_42F0E1EBA9EA3693_Table2(data[5:4]) ^ CRC64L_42F0E1EBA9EA3693_Table3(data[7:6]);

endfunction



function [63:0] CRC64L_42F0E1EBA9EA3693_Table0;

    input[1:0] data;

    case(data)

        2'b00: CRC64L_42F0E1EBA9EA3693_Table0 = 64'h0000000000000000; 2'b01: CRC64L_42F0E1EBA9EA3693_Table0 = 64'h42F0E1EBA9EA3693; 2'b10: CRC64L_42F0E1EBA9EA3693_Table0 = 64'h85E1C3D753D46D26; 2'b11: CRC64L_42F0E1EBA9EA3693_Table0 = 64'hC711223CFA3E5BB5;

        default: CRC64L_42F0E1EBA9EA3693_Table0 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;

    endcase

endfunction



function [63:0] CRC64L_42F0E1EBA9EA3693_Table1;

    input[1:0] data;

    case(data)

        2'b00: CRC64L_42F0E1EBA9EA3693_Table1 = 64'h0000000000000000; 2'b01: CRC64L_42F0E1EBA9EA3693_Table1 = 64'h493366450E42ECDF; 2'b10: CRC64L_42F0E1EBA9EA3693_Table1 = 64'h9266CC8A1C85D9BE; 2'b11: CRC64L_42F0E1EBA9EA3693_Table1 = 64'hDB55AACF12C73561;

        default: CRC64L_42F0E1EBA9EA3693_Table1 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;

    endcase

endfunction



function [63:0] CRC64L_42F0E1EBA9EA3693_Table2;

    input[1:0] data;

    case(data)

        2'b00: CRC64L_42F0E1EBA9EA3693_Table2 = 64'h0000000000000000; 2'b01: CRC64L_42F0E1EBA9EA3693_Table2 = 64'h663D78FF90E185EF; 2'b10: CRC64L_42F0E1EBA9EA3693_Table2 = 64'hCC7AF1FF21C30BDE; 2'b11: CRC64L_42F0E1EBA9EA3693_Table2 = 64'hAA478900B1228E31;

        default: CRC64L_42F0E1EBA9EA3693_Table2 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;

    endcase

endfunction



function [63:0] CRC64L_42F0E1EBA9EA3693_Table3;

    input[1:0] data;

    case(data)

        2'b00: CRC64L_42F0E1EBA9EA3693_Table3 = 64'h0000000000000000; 2'b01: CRC64L_42F0E1EBA9EA3693_Table3 = 64'hDA050215EA6C212F; 2'b10: CRC64L_42F0E1EBA9EA3693_Table3 = 64'hF6FAE5C07D3274CD; 2'b11: CRC64L_42F0E1EBA9EA3693_Table3 = 64'h2CFFE7D5975E55E2;

        default: CRC64L_42F0E1EBA9EA3693_Table3 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;

    endcase

endfunction





always [url=home.php?mod=space&uid=72445]@[/url] (posedge clk or negedge rst)

begin

    if (!rst)

    begin

        crc64 <= 64'hFFFFFFFFFFFFFFFF;

    end

    else

    begin

        CRC64L_42F0E1EBA9EA3693(crc64, data);

        outcrc64 <= crc64;

        crc64 <= crc64;

    end

end

endmodule