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Info: *******************************************************************<br />Info: Running Quartus II Analysis & Synthesis<br /> Info: Version 5.1 Build 176 10/26/2005 SJ Full Version<br /> Info: Processing started: Mon Jun 11 15:20:09 2007<br />Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fir -c fir<br />Info: Found 2 design units, including 1 entities, in source file fir.vhd<br /> Info: Found design unit 1: FIR-a<br /> Info: Found entity 1: FIR<br />Info: Elaborating entity "fir" for the top level hierarchy<br />Warning: Reduced register "process0~0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~1" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~4" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~6" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~8" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~10" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~12" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~14" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~16" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~18" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~20" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~22" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~24" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~26" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~28" with stuck data_in port to stuck value GND<br />Warning: Reduced register "process0~30" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[14]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[13]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[12]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[11]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[10]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[9]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[8]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[7]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[6]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[5]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[4]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[3]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[2]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[1]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[0]~reg0" with stuck data_in port to stuck value GND<br />Warning: Reduced register "Y[15]~reg0" with stuck data_in port to stuck value GND<br />Warning: Design contains 18 input pin(s) that do not drive logic<br /> Warning: No output dependent on input pin "CLK"<br /> Warning: No output dependent on input pin "RESET_N"<br /> Warning: No output dependent on input pin "X[0]"<br /> Warning: No output dependent on input pin "X[1]"<br /> Warning: No output dependent on input pin "X[2]"<br /> Warning: No output dependent on input pin "X[3]"<br /> Warning: No output dependent on input pin "X[4]"<br /> Warning: No output dependent on input pin "X[5]"<br /> Warning: No output dependent on input pin "X[6]"<br /> Warning: No output dependent on input pin "X[7]"<br /> Warning: No output dependent on input pin "H[0]"<br /> Warning: No output dependent on input pin "H[1]"<br /> Warning: No output dependent on input pin "H[2]"<br /> Warning: No output dependent on input pin "H[3]"<br /> Warning: No output dependent on input pin "H[4]"<br /> Warning: No output dependent on input pin "H[5]"<br /> Warning: No output dependent on input pin "H[6]"<br /> Warning: No output dependent on input pin "H[7]"<br />Info: Implemented 34 device resources after synthesis - the final resource count might be different<br /> Info: Implemented 18 input pins<br /> Info: Implemented 0 output pins<br /> Info: Implemented 16 bidirectional pins<br />Info: Quartus II Analysis & Synthesis was successful. 0 errors, 51 warnings<br /> Info: Processing ended: Mon Jun 11 15:20:10 2007<br /> Info: Elapsed time: 00:00:02<br />Info: *******************************************************************<br />Info: Running Quartus II Fitter<br /> Info: Version 5.1 Build 176 10/26/2005 SJ Full Version<br /> Info: Processing started: Mon Jun 11 15:20:12 2007<br />Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fir -c fir<br />Info: Selected device EP1S10B672C6 for design "fir"<br />Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time<br />Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices<br /> Info: Device EP1S20B672C6 is compatible<br /> Info: Device EP1S25B672C6 is compatible<br />Info: No exact pin location assignment(s) for 34 pins of 34 total pins<br /> Info: Pin CLK not assigned to an exact location on the device<br /> Info: Pin RESET_N not assigned to an exact location on the device<br /> Info: Pin X[0] not assigned to an exact location on the device<br /> Info: Pin X[1] not assigned to an exact location on the device<br /> Info: Pin X[2] not assigned to an exact location on the device<br /> Info: Pin X[3] not assigned to an exact location on the device<br /> Info: Pin X[4] not assigned to an exact location on the device<br /> Info: Pin X[5] not assigned to an exact location on the device<br /> Info: Pin X[6] not assigned to an exact location on the device<br /> Info: Pin X[7] not assigned to an exact location on the device<br /> Info: Pin H[0] not assigned to an exact location on the device<br /> Info: Pin H[1] not assigned to an exact location on the device<br /> Info: Pin H[2] not assigned to an exact location on the device<br /> Info: Pin H[3] not assigned to an exact location on the device<br /> Info: Pin H[4] not assigned to an exact location on the device<br /> Info: Pin H[5] not assigned to an exact location on the device<br /> Info: Pin H[6] not assigned to an exact location on the device<br /> Info: Pin H[7] not assigned to an exact location on the device<br /> Info: Pin Y[0] not assigned to an exact location on the device<br /> Info: Pin Y[1] not assigned to an exact location on the device<br /> Info: Pin Y[2] not assigned to an exact location on the device<br /> Info: Pin Y[3] not assigned to an exact location on the device<br /> Info: Pin Y[4] not assigned to an exact location on the device<br /> Info: Pin Y[5] not assigned to an exact location on the device<br /> Info: Pin Y[6] not assigned to an exact location on the device<br /> Info: Pin Y[7] not assigned to an exact location on the device<br /> Info: Pin Y[8] not assigned to an exact location on the device<br /> Info: Pin Y[9] not assigned to an exact location on the device<br /> Info: Pin Y[10] not assigned to an exact location on the device<br /> Info: Pin Y[11] not assigned to an exact location on the device<br /> Info: Pin Y[12] not assigned to an exact location on the device<br /> Info: Pin Y[13] not assigned to an exact location on the device<br /> Info: Pin Y[14] not assigned to an exact location on the device<br /> Info: Pin Y[15] not assigned to an exact location on the device<br />Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements<br /> Info: Assuming a global fmax requirement of 1 MHz<br /> Info: Not setting a global tsu requirement<br /> Info: Not setting a global tco requirement<br /> Info: Not setting a global tpd requirement<br />Info: Performing register packing on registers with non-logic cell location assignments<br />Info: Completed register packing on registers with non-logic cell location assignments<br />Info: Completed User Assigned Global Signals Promotion Operation<br />Info: Completed Auto Global Promotion Operation<br />Info: Starting register packing<br />Info: Started Fast Input/Output/OE register processing<br />Info: Finished Fast Input/Output/OE register processing<br />Info: Start inferring scan chains for DSP blocks<br />Info: Inferring scan chains for DSP blocks is complete<br />Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option<br />Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density<br />Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks<br />Info: Finished register packing<br />Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement<br /> Info: Number of I/O pins in group: 34 (unused VREF, 3.30 VCCIO, 18 input, 0 output, 16 bidirectional)<br /> Info: I/O standards used: LVTTL.<br />Info: I/O bank details before I/O pin placement<br /> Info: Statistics of I/O banks<br /> Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available<br /> Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available<br /> Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 43 pins available<br /> Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 44 pins available<br /> Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available<br /> Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available<br /> Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 45 pins available<br /> Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 44 pins available<br /> Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 6 pins available<br /> Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 0 pins available<br /> Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 6 pins available<br /> Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 0 pins available<br />Info: Fitter placement preparation operations beginning<br />Info: Fitter placement preparation operations ending: elapsed time is 00:00:00<br />Info: Fitter placement operations beginning<br />Info: Fitter placement was successful<br />Info: Fitter placement operations ending: elapsed time is 00:00:00<br />Info: Fitter routing operations beginning<br />Info: Fitter routing operations ending: elapsed time is 00:00:00<br />Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.<br /> Info: Optimizations that may affect the design's routability were skipped<br /> Info: Optimizations that may affect the design's timing were skipped<br />Info: Completed Fixed Delay Chain Operation<br />Info: Started post-fitting delay annotation<br />Info: Delay annotation completed successfully<br />Info: Completed Auto Delay Chain Operation<br />Warning: Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results<br /> Info: Pin Y[0] has a permanently enabled output enable<br /> Info: Pin Y[1] has a permanently enabled output enable<br /> Info: Pin Y[2] has a permanently enabled output enable<br /> Info: Pin Y[3] has a permanently enabled output enable<br /> Info: Pin Y[4] has a permanently enabled output enable<br /> Info: Pin Y[5] has a permanently enabled output enable<br /> Info: Pin Y[6] has a permanently enabled output enable<br /> Info: Pin Y[7] has a permanently enabled output enable<br /> Info: Pin Y[8] has a permanently enabled output enable<br /> Info: Pin Y[9] has a permanently enabled output enable<br /> Info: Pin Y[10] has a permanently enabled output enable<br /> Info: Pin Y[11] has a permanently enabled output enable<br /> Info: Pin Y[12] has a permanently enabled output enable<br /> Info: Pin Y[13] has a permanently enabled output enable<br /> Info: Pin Y[14] has a permanently enabled output enable<br /> Info: Pin Y[15] has a permanently enabled output enable<br />Warning: Following 16 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results<br /> Info: Pin Y[0] has GND driving its datain port<br /> Info: Pin Y[1] has GND driving its datain port<br /> Info: Pin Y[2] has GND driving its datain port<br /> Info: Pin Y[3] has GND driving its datain port<br /> Info: Pin Y[4] has GND driving its datain port<br /> Info: Pin Y[5] has GND driving its datain port<br /> Info: Pin Y[6] has GND driving its datain port<br /> Info: Pin Y[7] has GND driving its datain port<br /> Info: Pin Y[8] has GND driving its datain port<br /> Info: Pin Y[9] has GND driving its datain port<br /> Info: Pin Y[10] has GND driving its datain port<br /> Info: Pin Y[11] has GND driving its datain port<br /> Info: Pin Y[12] has GND driving its datain port<br /> Info: Pin Y[13] has GND driving its datain port<br /> Info: Pin Y[14] has GND driving its datain port<br /> Info: Pin Y[15] has GND driving its datain port<br />Info: Quartus II Fitter was successful. 0 errors, 2 warnings<br /> Info: Processing ended: Mon Jun 11 15:20:22 2007<br /> Info: Elapsed time: 00:00:11<br />Info: *******************************************************************<br />Info: Running Quartus II Assembler<br /> Info: Version 5.1 Build 176 10/26/2005 SJ Full Version<br /> Info: Processing started: Mon Jun 11 15:20:24 2007<br />Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off fir -c fir<br />Info: Quartus II Assembler was successful. 0 errors, 0 warnings<br /> Info: Processing ended: Mon Jun 11 15:20:29 2007<br /> Info: Elapsed time: 00:00:05<br />Info: *******************************************************************<br />Info: Running Quartus II Timing Analyzer<br /> Info: Version 5.1 Build 176 10/26/2005 SJ Full Version<br /> Info: Processing started: Mon Jun 11 15:20:30 2007<br />Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fir -c fir --timing_analysis_only<br />Warning: No paths found for timing analysis<br />Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning<br /> Info: Processing ended: Mon Jun 11 15:20:31 2007<br /> Info: Elapsed time: 00:00:01<br />Info: Quartus II Full Compilation was successful. 0 errors, 54 warnings
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