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entity delay14 is<br /> port(<br /> d : in std_logic;<br /> clk : in std_logic;<br /> q : out std_logic<br /> );<br />end delay14;<br /><br />architecture vr2 of delay14 is<br /> signal cn : std_logic_vector(10 downto 0) := (others=>'0');<br /> signal flag : std_logic;<br />begin<br /> p1:process(clk) -- process(clk,d)<br /> begin<br /> if (clk'event and clk='1')then<br /> if(d='1' and cn="00000000000" and flag='0') then<br /> flag <= '1'; -- 结束时，d='1'一直成立，故增加个标志<br /> cn <= "10000000000";<br /> elsif(cn>"00000000000")then<br /> cn <= cn-'1';<br /> else<br /> cn <="00000000000"; flag <= '0';<br /> end if;<br /> end if;<br /> end process p1;<br /> q <='0' when cn="00000000000" else '1'; <br /> <br />end vr2;<br />这个程序怎么 不能实现连续 １０２４ 个高电平后再变低电平？？ |
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