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代码如下：<br />其中clk和从in.txt读入的数据都是对的，从modelsim上都可以看出来，就是中间一段的process中GPS_PULSE和aclr没有执行，从波形上看一直是高‘1’。不知道怎么回事，编译没有错误<br />LIBRARY ieee; <br />--use ieee.numeric_std.all; <br />USE ieee.std_logic_1164.all; <br />use ieee.std_logic_unsigned.all;<br />use ieee.std_logic_arith.all;<br />use ieee.std_logic_textio.all;<br />library std;<br />USE STD.TEXTIO.ALL;<br />ENTITY pncodesearch_vhd_tst IS<br />END pncodesearch_vhd_tst;<br />ARCHITECTURE pncodesearch_arch OF pncodesearch_vhd_tst IS<br />-- constants <br />constant ClockPeriod : TIME := 40 ns; <br />-- signals <br />--type LINE is access integer; <br />SIGNAL aclr : STD_LOGIC;<br />SIGNAL acq : STD_LOGIC_VECTOR(1 DOWNTO 0);<br />SIGNAL catched : STD_LOGIC;<br />SIGNAL clk : STD_LOGIC;<br />SIGNAL d : STD_LOGIC_VECTOR(7 DOWNTO 0);<br />SIGNAL dout : STD_LOGIC_VECTOR(35 DOWNTO 0);<br />SIGNAL GPS_PULSE : STD_LOGIC;<br />SIGNAL matched : STD_LOGIC;<br />SIGNAL pnoffset : STD_LOGIC_VECTOR(15 DOWNTO 0);<br /><br />COMPONENT pncodesearch<br /> PORT (<br /> aclr : IN STD_LOGIC;<br /> acq : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);<br /> catched : OUT STD_LOGIC;<br /> clk : IN STD_LOGIC;<br /> d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);<br /> dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);<br /> GPS_PULSE : IN STD_LOGIC;<br /> matched : OUT STD_LOGIC;<br /> pnoffset : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)<br /> );<br />END COMPONENT;<br />BEGIN<br /> i1 : pncodesearch<br /> PORT MAP (<br />-- list connections between master ports and signals<br /> aclr => aclr,<br /> acq => acq,<br /> catched => catched,<br /> clk => clk,<br /> d => d,<br /> dout => dout,<br /> GPS_PULSE => GPS_PULSE,<br /> matched => matched,<br /> pnoffset => pnoffset<br /> );<br /> <br />--clk <= not clk after ClockPeriod / 2; <br /> clkgen: process<br />begin<br /> wait for (ClockPeriod / 2);<br /> clk <= '1';<br /> wait for (ClockPeriod / 2);<br /> clk <= '0';<br /> end process;<br /> <br />init :process <br />-- variable declarations <br />begin <br /> GPS_PULSE <= '1';<br /> aclr <= '1';<br /> wait for 40 ns;<br /> GPS_PULSE <= '0';<br /> aclr <= '0';<br />end process ; -- code that executes only once <br /> <br />always : PROCESS <br />-- optional sensitivity list <br />-- ( ) <br />-- variable declarations<br /> FILE inputfile: TEXT open read_mode is "D:\altera\temp\pncodesearch_4\simulation\modelsim\in.txt"; <br /> VARIABLE l: LINE; <br /> VARIABLE r :std_logic_vector(7 downto 0); <br /> -- variable good_number : boolean;<br /> <br />BEGIN <br /> while not endfile(inputfile)loop<br /> wait until clk'event and clk='1';<br /> readline(inputfile,l); <br /> read(l,r);<br /> d<=r; <br /> <br /> end loop; <br /> -- code executes for every event on sensitivity list <br />--WAIT; <br />END PROCESS;<br />--output : PROCESS<br />-- FILE RESULT_file: TEXT open write_mode is "out.txt";<br />-- VARIABLE l: LINE;<br />-- VARIABLE r :std_logic_vector(7 downto 0); <br />--begin<br />-- WAIT UNTIL ready='1';<br /> <br />--END PROCESS output; <br />END pncodesearch_arch;<br /> |
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