void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
// CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);//0X10;48MHZ
IFCONFIG |= 0xCB;//异步，从FIFO模式.11001011
SYNCDELAY;
REVCTL = 0x03; // enable the external master
SYNCDELAY;
// config the endpoints direction
EP1OUTCFG = 0xA0;//enable and bulk type
SYNCDELAY;
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xA0;//out,bulk,512,double
SYNCDELAY;
EP4CFG &= 0x7F;
SYNCDELAY;
EP6CFG = 0xE0;//enable IN bulk 512 double buffer
SYNCDELAY;
EP8CFG &= 0x7F;
SYNCDELAY;
//reset the fifos
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
///////////////////////////////////////////////////////////////////
OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
//config the endpoint6
EP2FIFOCFG = 0x11;//EP2 IS AUTOOUT=1 ZEROLEN=1 WORDIDE=1 配置EP2自动方式16位总
SYNCDELAY;//添加EP2
EP6FIFOCFG = 0x0D;//EP6 IS AUTOIN =1 ZEROLEN=1 WORDIDE=1 配置EP6自动方式16位总
SYNCDELAY;
//-------------------------
INPKTEND = 0x06;
SYNCDELAY;
INPKTEND = 0x06;
SYNCDELAY;
INPKTEND = 0x06;
SYNCDELAY;
INPKTEND = 0x06;
SYNCDELAY;
//-------------------tiao ji IN depth_1204---------------------
EP6AUTOINLENH = 0x02; //set the packet size 512
SYNCDELAY;
EP6AUTOINLENL = 0x00;//EP6 recevie 10 num (16bit)LYF
SYNCDELAY;
PINFLAGSAB = 0xe8; //F,FLAGA IS THE FIFO2 EF,FLAGb IS THE FIFO6 FULL FLAG
SYNCDELAY;
PORTACFG = 0x00;//PA7 pin as a port pin,not as a fifo flag;
SYNCDELAY;
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low PKTEND OR SLOE SLWR LOW AVTIVE
SYNCDELAY;
}
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