有没有牛人写写这个testbench??
module UART(rxd,clock,out,end_flag);
input clock; //????
input rxd; //??
output[7:0] out; //????8???
output end_flag;
reg[7:0] out;
reg end_flag;
reg recclk;//16??9600???
reg[8:0]divcnt;//????
reg[9:0]data_buf; //??????
reg[3:0]cnt;
reg[3:0]bitpos; //???????
reg[7:0]sbuf;
reg[1:0]state;
//-------------------------------------------------------------------------//
parameter st0=2'b00, //?????
st1=2'b01,
st2=2'b11;
// st3=2'b10;
//-------------------------------------------------------------------------//
always@(posedge clock) //????325? ??9600 16????
begin //????162? ??19200 16????
if(divcnt<9'd162)
begin
divcnt=divcnt+1'b1;
recclk=1'b0;
end
else
begin
divcnt=1'b0;
recclk=1'b1;
end
end
//-------------------------------------------------------------------------//
always@(posedge recclk)//16??9600???
begin
case(state)
st0:begin
// end_flag=1'b1;
end_flag=1'b0;
if(rxd==1'b1)
begin
cnt=4'h0;
state=st0;//??????
end
else
begin
cnt=cnt+1'b1;
end
if(cnt==4'h2)
begin
state=st1;
cnt=4'h0;
bitpos=0;
end
end
//--------------------//
st1:begin
if(cnt==4'hf)
begin
cnt=4'h0;
data_buf[bitpos]=rxd;
bitpos=bitpos+1'b1;
if(bitpos==4'd9)//9???
begin
bitpos=4'd0;
state=st2;
end
end
else
begin
cnt=cnt+1'b1;
end
end
//---------------------//
st2:begin//????????
// end_flag=1'b0; //??
end_flag=1'b01;//??????????
sbuf=data_buf[7:0];
out=sbuf;
state=st0;
end
default:state=st0;
endcase
end
endmodule
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