[matlab] EDK integration with ISE project(英文,zz)

[复制链接]
 楼主| AutoESL 发表于 2011-10-15 21:37 | 显示全部楼层 |阅读模式
本帖最后由 AutoESL 于 2011-10-15 22:44 编辑

Design Flow
Recommended FlowIt's recommended to add EDK project file ”.xmp” into ISE project directly.
  • ISE → Add Source → xmp file
  • Insert wrapper by
    • Insert <EDK Proj>/hdl/system_stub.v. This file is generated by the initial phase of “Generate Netlists” in EDK.
    • ISE → Select the xmp file → Generate Instantiation Templates
  • Assign the software project to initialize BRAM in EDK project
    • For XPS build-in projects, select “Mark to initialize BRAM”
    • For SDK projects, add a new elf only project which directs to SDK generated ELF file.

Alternative Flow
  • Open XMP file, set InsertNoPad:1 and regenerate EDK subsystem netlist End of added content
  • Add End of added content Start of deleted contentNote: End of deleted content Start of added content/hdl/system_stub.v to ISE project. EDK subsystem is a blackbox. End of added content
  • Synthesize the design with Synplify and get an EDF netlist. End of added content
  • Add EDF, ucf, BMM, ELF/MEM files to ISE project. End of added content
  • Set translate option -sd = End of added content Start of added content/implementation End of added content
  • Run whole implementation process. Bitgen will generate the bit file which includes the content of ELF/MEM.

Notes
Synthesize with XST
  • From 12.2, ISE won't copy EDK netlists to ISE project directory. It's necessary to set
XST "Macro Search Path" (-sd) = <EDK Project>/implementationXST read cores = trueNgdBuild "Macro Search Path" (-sd) = <EDK Project>/implementation
Synthesize with Synplify
  • Set
NgdBuild "Macro Search Path" (-sd) = <EDK Project>/implementation
  • When EDK IP includes I/O Buffers, refer to AR4508 for how to disable Synplify inserting I/O buffers for selected I/O.

BMM File Modification
  • ISE and XST based system will generate BMM file accordingly
  • Alternative Flow needs to update BMM file manually
    • Copy BMM file in EDK directory to ISE project directory and add it to ISE project
    • Add top level hierarchy to the BRAM name in the BMM file
    • Full BRAM name can be found in synthesis results, which can be opened by ISE or PlanAhead
 楼主| AutoESL 发表于 2011-10-15 21:38 | 显示全部楼层
GoldSunMonkey 发表于 2011-10-15 22:46 | 显示全部楼层
嗯,A,翻译翻译呗。
 楼主| AutoESL 发表于 2011-10-15 22:48 | 显示全部楼层
太简单了,有必要翻译吗?没必要:D
GoldSunMonkey 发表于 2011-10-15 22:49 | 显示全部楼层
;P太有了。
 楼主| AutoESL 发表于 2011-10-15 22:52 | 显示全部楼层
得锻炼PFGA工程师的E文能力:)
GoldSunMonkey 发表于 2011-10-15 23:09 | 显示全部楼层
;P应该出考试题目
 楼主| AutoESL 发表于 2011-10-16 00:05 | 显示全部楼层
猴哥出几个
您需要登录后才可以回帖 登录 | 注册

本版积分规则

个人签名:天使宝贝 博客IT人生 From C/C++/SystemC to Xilinx FPGA

0

主题

2517

帖子

3

粉丝
快速回复 在线客服 返回列表 返回顶部
个人签名:天使宝贝 博客IT人生 From C/C++/SystemC to Xilinx FPGA

0

主题

2517

帖子

3

粉丝
快速回复 在线客服 返回列表 返回顶部