I am working on design of APB master and slave connected back to back. Slave component has simple reg with 16 locations
As per APB, for READ/WRITE transaction from master I am generating PSEL = 1 in the first clock cycle and then PENABLE = 1 in the next clock cycle.
During the two clock cycles, PADDR, PWDATA, PWRITE signals does not change. Here APB slave drives PREADY always HIGH. So the PENABLE goes to \'0\' in the second clock cycle as per the protocol.
Question here is when should APB slave SAMPLE the Control/Data Signals from Master for both READ/WRITE transfers ? Is it in the SETUP phase or the ACCESS phase.
We need to drive the PREADY and PSLVERR and the PRDATA from slave at the same clock for the read transfer (which should happen in the ACCESS phase here).
Hope my query is clear here. Please share inputs. |
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