数据手册里面有讲到
There is also an option for running the 4xPLL on any of
the clock sources in the input frequency range of 4 to
16 MHz.
The PLL is enabled by setting the PLLCFG bit
(CONFIG1H<4>) or the PLLEN bit (OSCTUNE<6>).
For the EC and HS modes, the PLLEN (software) or
PLLCFG (CONFIG1H<4>) bit can be used to enable
the PLL.
For the INTIOx modes (HF-INTOSC):
• Only the PLLEN can enable the PLL (PLLCFG is
ignored).
• When the oscillator is configured for the internal
oscillator (FOSC<3:0> = 100x), the PLL can be
enabled only when the HF-INTOSC frequency is
4, 8 or 16 MHz.
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