本帖最后由 entepino 于 2012-12-11 16:58 编辑
很简单的一个程序，7位串转并，连复位信号都没有。为何就会出现这么多警告阿？
端口：
SDI_IN : in std_logic;
CS_IN : in std_logic;
SCK_IN : in std_logic;
CLK64M : in std_logic;
PData_OUT : out std_logic_vector(7 downto 0);
信号：
signal q_temp : std_logic_vector(7 downto 0);
RecProcess: process(SCK_IN,CS_IN,SDI_IN,sdi_cnt,q_temp)
begin
if CS_IN = '0' then
if (SCK_IN'event and SCK_IN = '0') then --receive data
for i in 7 downto 1 loop
q_temp(i)<=q_temp(i-1);
end loop;
q_temp(0) <= SDI_IN;
else
null;
end if;
if (sdi_cnt = 8) then --after receiving data , send data to signal q1_temp;
PData_OUT <= q_temp;
sdi_cnt <= 0;
else
sdi_cnt <= sdi_cnt+1;
end if;
end if;
end process RecProcess;
简单程序高分求消除警告。
简单程序高分求消除警告。 1、 Warning (10631): VHDL Process Statement warning at SPI001.vhd(85): inferring latch(es) for signal or variable "PData_OUT", which holds its previous value in one or more paths through the process 2、Warning (10631): VHDL Process Statement warning at SPI001.vhd(85): inferring latch(es) for signal or variable "sdi_cnt", which holds its previous value in one or more paths through the process 3、Warning: Feature LogicLock is not available with your current license 4、Warning: Timing Analysis is analyzing one or more combinational loops as latches Warning: Node "sdi_cnt[0]" is a latch Warning: Node "sdi_cnt[2]" is a latch Warning: Node "sdi_cnt[4]" is a latch Warning: Node "sdi_cnt[1]" is a latch Warning: Node "sdi_cnt[3]" is a latch Warning: Node "sdi_cnt[6]" is a latch Warning: Node "sdi_cnt[5]" is a latch Warning: Node "PData_OUT[0]$latch" is a latch Warning: Node "PData_OUT[1]$latch" is a latch Warning: Node "PData_OUT[2]$latch" is a latch Warning: Node "PData_OUT[3]$latch" is a latch Warning: Node "PData_OUT[4]$latch" is a latch Warning: Node "PData_OUT[5]$latch" is a latch Warning: Node "PData_OUT[6]$latch" is a latch Warning: Node "PData_OUT[7]$latch" is a latch 5、Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "SCK_IN" is an undefined clock Info: Assuming node "CS_IN" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin. 6、Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "sdi_cnt[5]" as buffer Info: Detected ripple clock "sdi_cnt[6]" as buffer Info: Detected ripple clock "sdi_cnt[3]" as buffer Info: Detected ripple clock "sdi_cnt[1]" as buffer Info: Detected ripple clock "sdi_cnt[4]" as buffer Info: Detected ripple clock "sdi_cnt[2]" as buffer Info: Detected ripple clock "sdi_cnt[0]" as buffer Info: Detected gated clock "PData_OUT[7]~0" as buffer Info: Detected gated clock "Equal3~1" as buffer Info: Detected gated clock "Equal3~0" as buffer | 
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