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FPGA内部才有RAM吧!并且要自己写程序才有哦.<br />用Verilog 语言写的dual-RAM<br />大家看分析一下<br />module ram2kx8 (CLK,WEA,WEB,ADDRA,ADDRB,DINA,DINB,DOUTA,DOUTB);//2k block ram<br /> input CLK;<br /> input WEA;<br /> input WEB;<br /> input [10:0]ADDRA;<br /> input [10:0]ADDRB;<br /> input [7:0]DINA;<br /> input [7:0]DINB;<br /> output [7:0]DOUTA;<br /> output [7:0]DOUTB;<br /> reg [7:0]buffer[2047:0];<br /> always @ (posedge CLK)begin<br /> if(WEA)begin<br /> buffer[ADDRA]<=DINA;<br /> end<br /> if(WEB)begin<br /> buffer[ADDRB]<=DINB;<br /> end<br /> end<br /> always @ (posedge CLK)begin<br /> DOUTA<=buffer[ADDRA];<br /> DOUTB<=buffer[ADDRB];<br /> end<br />endmodule
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