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library ieee;<br />use ieee.std_logic_1164.all;<br /><br />entity or2 is <br /> port(<br /> a1,b1 : in std_logic;<br /> c1 : out std_logic<br /> );<br />end or2;<br /><br />architecture one of or2 is<br /> begin<br /> c1<=(a1 or b1);<br />end one;<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br /><br />entity h_adder is<br /> port(<br /> a,b : in std_logic;<br /> co,so : out std_logic<br /> );<br />end h_adder;<br /><br />architecture one of h_adder is<br /> begin<br /> so<=(a or b) and (a nand b);<br /> co<=not (a nand b);<br />end one;<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br /><br />entity f_adder is<br /> port(<br /> ain,bin,cin : in std_logic;<br /> cout,sum : out std_logic<br /> );<br />end f_adder;<br /><br />architecture one of f_adder is<br /><br /> component or2<br /> port(<br /> a1,b1 : in std_logic;<br /> c1 : out std_logic<br /> );<br /> end component;<br /> <br /> component h_adder<br /> port(<br /> a,b : in std_logic;<br /> co,so : out std_logic<br /> );<br /> end component;<br /> <br /> <br /> signal d,e,f : std_logic;<br /> begin<br /> u1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e);<br /> u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>sum);<br /> u3 : or2 port map(a1=>d,b1=>f,c1=>cout);<br />end one;<br />分别保存后，在综合的时候出现<br /> symbolic name "a1"is not a port of "or2"in a vhdl design file<br />symbolic name "b1"is not a port of "or2"in a vhdl design file<br />symbolic name "c1"is not a port of "or2"in a vhdl design file<br />暑假自学中有点迷茫哈，谢谢大虾指导。 |
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