请大家帮忙看看这段VHDL哪里有问题？

小弟是初学者，才写的1位全加器的代码，用MAX＋plus的，老是报这样的错：node'\mux21a:u2\:23.in1'&nbsp;missing&nbsp;source,&nbsp;麻烦大家帮忙看看<br />，谢谢！<br />library&nbsp;ieee;<br />use&nbsp;ieee.std_logic_1164.all;<br />entity&nbsp;muxk&nbsp;is&nbsp;<br />port&nbsp;(a1,a2,a3,s0,s1:&nbsp;in&nbsp;std_logic;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;outy&nbsp;:&nbsp;out&nbsp;std_logic);<br />end&nbsp;entity&nbsp;muxk;<br />architecture&nbsp;a&nbsp;of&nbsp;muxk&nbsp;is&nbsp;<br />component&nbsp;mux21a<br />port&nbsp;(&nbsp;a,b,s:&nbsp;in&nbsp;std_logic;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;y:&nbsp;out&nbsp;std_logic);<br />end&nbsp;component&nbsp;;<br />signal&nbsp;tmp:&nbsp;std_logic;<br />begin<br />u1:&nbsp;mux21a&nbsp;port&nbsp;map&nbsp;(&nbsp;a=&gta2,&nbsp;b=&gta3,s=&gts0);<br />u2:&nbsp;mux21a&nbsp;port&nbsp;map&nbsp;(&nbsp;a=&gta1,&nbsp;b=&gttmp,&nbsp;s=&gts1,y=&gtouty);<br />end&nbsp;architecture&nbsp;a;<br /><br />library&nbsp;ieee;<br />use&nbsp;ieee.std_logic_1164.all;<br />entity&nbsp;mux21a&nbsp;is<br />port(a,b&nbsp;:&nbsp;in&nbsp;&nbsp;std_logic;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;s:&nbsp;in&nbsp;std_logic;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;y:&nbsp;out&nbsp;std_logic);<br />end&nbsp;mux21a&nbsp;;<br />architecture&nbsp;b_mux21a&nbsp;of&nbsp;mux21a&nbsp;is<br />begin<br />&nbsp;&nbsp;y&lt=(a&nbsp;and&nbsp;(not&nbsp;s))&nbsp;or&nbsp;(b&nbsp;and&nbsp;s);<br />end&nbsp;b_mux21a;<br /><br />library&nbsp;ieee;<br />use&nbsp;ieee.std_logic_1164.all;<br />entity&nbsp;mux21a&nbsp;is<br />port(a,b&nbsp;:&nbsp;in&nbsp;&nbsp;std_logic;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;s:&nbsp;in&nbsp;std_logic;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;y:&nbsp;out&nbsp;std_logic);<br />end&nbsp;mux21a&nbsp;;<br />architecture&nbsp;b_mux21a&nbsp;of&nbsp;mux21a&nbsp;is<br />begin<br />&nbsp;&nbsp;process&nbsp;(a,b,s)<br />begin<br />if&nbsp;s='0'&nbsp;then&nbsp;y&lt=a;<br />else&nbsp;y&lt=b;<br />end&nbsp;if;<br />end&nbsp;process;<br />end&nbsp;b_mux21a;<br />

你调用的两个模块都取名为mux21a，应该不行吧

改了名字，也报同样的错啊

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;这个也叫全加器吗?怎么偶怎么看都象是错误的三算一器件?惭愧,!

end&nbsp;architecture&nbsp;a;<br />

&nbsp;&nbsp;&nbsp;&nbsp;你调用的是两个模块,而你却例化了一个模块的端口,第二模的端口找不到当然就出错了哦<br />&nbsp;&nbsp;&nbsp;&nbsp;还有,两个模块的名字最好不要相同,加以区分可读性也增强了!<br />&nbsp;&nbsp;&nbsp;&nbsp;

谢谢大家