LIBRARY IEEE;<br />USE IEEE.STD_LOGIC_1164.ALL;<br />USE IEEE.STD_LOGIC_UNSIGNED.ALL; <br /><br />ENTITY SPDA IS<br /> PORT ( CLK,PHSEL0,PHSEL1 :IN STD_LOGIC;<br /> SDAA :OUT INTEGER RANGE 0 TO 127;<br /> PDAA :OUT INTEGER RANGE 0 TO 127);<br />END;<br /><br />ARCHITECTURE BEHV OF SPDA IS<br /> SIGNAL PHSEL :STD_LOGIC_VECTOR(1 DOWNTO 0);<br /> SIGNAL SDAA_S :INTEGER RANGE 0 TO 127 :=0;<br /> SIGNAL PDAA_S :INTEGER RANGE 0 TO 127 :=0; <br />BEGIN<br /> PHSEL <= PHSEL1 & PHSEL0;<br /> PROCESS(CLK)<br /> BEGIN<br /> IF ( CLK'EVENT AND CLK='1' ) THEN<br /> SDAA_S <= SDAA_S+1;<br /> PDAA_S <= PDAA_S+1;<br /> END IF;<br /> END PROCESS;<br /> SDAA <= SDAA_S;<br />-- CASE (PHSEL) IS <br />-- WHEN "00" =><br />-- PDAA <= PDAA_S; <br />-- WHEN "01" =><br />-- PDAA <= PDAA_S+32; <br />-- WHEN "10" =><br />-- PDAA <= PDAA_S+64; <br />-- WHEN "11" =><br />-- PDAA <= PDAA_S+32; <br />-- END CASE;<br />END BEHV; |
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