library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br />entity vhdl1 is <br />port(s1:in std_logic_vector(3 downto 0);<br /> s0:in std_logic_vector(3 downto 0) ;<br /> min1:in std_logic_vector(3 downto 0);<br /> min0:in std_logic_vector(3 downto 0);<br /> cout:out std_logic);<br /> end vhdl1;<br />architecture xuan of vhdl1 is<br />signal m0:std_logic;<br />signal m1:std_logic;<br />signal m2:std_logic;<br />signal m3:std_logic;<br />begin<br />p_a:process(min1)<br />begin<br />if min1="0101" then m0<='1';<br />else m0<='0';<br />end if ;<br />end process p_a;<br />p_b:process(min0)<br />begin <br />if min0="1001" then m1<='1';<br />else m1<='0';<br />end if ;<br />end process p_b;<br />p_c:process(s1)<br />begin <br />if s1="0101" then m2<='1';<br />else m2<='0';<br />end if ;<br />end process p_c;<br />p_d:process (s0)<br />begin<br />case s0 is<br />when"0001"=>m3<='1';<br />when"0011"=>m3<='1';<br />when"0101"=>m3<='1';<br />when"0111"=>m3<='1';<br />when others=>m3<='0';<br />end case;<br />end process p_d;<br />p_e:process(m0,m1,m2,m3)<br /> begin<br /> if m0='1' and m1='1' and m2='1' and m3='1' then<br /> cout<='1';<br /> else cout<='0';<br /> end if ;<br /> end process p_e;<br />end xuan;<br /> |
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