以下配置供参考:
// - Data/Address MUX = Disable
// - Memory Type = CRAM (Cellular RAM or PSRAM)
// - Data Width = 16bit
// - Write Operation = Enable
// - Extended Mode = Disable
// - Asynchronous Wait = Disable
// - WaitSignalPolarity = Low
// - BurstAccessMode = Enable
FSMC_Bank1->BTCR[0] = FSMC_DataAddressMux_Disable | FSMC_MemoryType_CRAM |
FSMC_MemoryDataWidth_16b | FSMC_WriteOperation_Enable |
FSMC_ExtendedMode_Disable | FSMC_AsyncWait_Disable |
FSMC_WaitSignalPolarity_Low | FSMC_BurstAccessMode_Enable |
FSMC_WaitSignalActive_DuringWaitState;
// timing setting
FSMC_Bank1->BTCR[1] = 0x00000101 | FSMC_CLK_DIV_2;
// - BANK 1 (of NOR/SRAM Bank 1~4) is enabled
FSMC_Bank1->BTCR[0] |= 0x0001;
|