一个简单的VerilogHDL程序仿真波形出错，求解！

先上源代码：
    module counter4(clk,rst,out);input clk,rst;
output[3:0] out;
reg[3:0] out;
always @(posedge clk)
begin
if(rst) out<=0;
else
out <= out+1;
//out<=1;
end
endmodule
仿真的波形截图

[img][/img]

file:///C:/Documents%20and%20Settings/Administrator/%E6%A1%8C%E9%9D%A2/%E6%9C%AA%E5%91%BD%E5%90%8D.bmp

[url]file:///C:/Documents%20and%20Settings/Administrator/%E6%A1%8C%E9%9D%A2/%E6%9C%AA%E5%91%BD%E5%90%8D.bmp[/url]

图我发不上去，在OUT变化时，有一段时间是不确定的状态，或是状态不对！

rst 低电平有效
always @(posedge clk or negedge rst)
begin
if(~rst)
       out<=4'b0;
else
       out <= out+4'b1;
end