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-- Company:
-- Engineer:
--
-- Create Date: 10:50:25 04/01/2010
-- Design Name:
-- Module Name: contorl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity contorl is
Port ( fifordclk,sramrd,sramwr : out STD_LOGIC;
rdfifodata : in STD_LOGIC_VECTOR (15 downto 0);
test : buffer STD_LOGIC;
vsync,hsync : out STD_LOGIC;
dtmg : buffer STD_LOGIC;
fiforden:out STD_LOGIC;
tftout : out STD_LOGIC_VECTOR (15 downto 0);
ramaddrout : out STD_LOGIC_VECTOR (18 downto 0);
clk30m,clk60m0,clk60m90,reset : in STD_LOGIC;
end contorl;
architecture Behavioral of contorl is
signal hcount:integer range 0 to 2047;
signal vcount,sramcontrolcount:integer range 0 to 1023;
signal rdaddr:integer range 0 to 480000;
signal displayen,rden,wren:STD_LOGIC;
signal readaddr:STD_LOGIC_VECTOR (17 downto 0);
signal colordata:STD_LOGIC_VECTOR (15 downto 0);
begin
--颜色输出，行同步，场同步输出
dotout:process(clk30m,reset)
variable dtmgbuf,dtmgenable: std_logic;
begin
if reset='0' then
hcount<=0;
vcount<=0;
dtmgbuf:='0';
hsync<='1';
vsync<='1';
fiforden<='0';
elsif rising_edge(clk30m) then
hcount<=hcount+1;
end if;
if hcount<128 then
hsync<='0';
else
hsync<='1';
if hcount>214 then
fiforden<='1';
end if;
if hcount>215 then
if (hount mod 1)=0 then
tftout<=rdfifodata(7 downto 0);
else
tftout<=rdfifodata(15 downto 7);
end if;
dtmgbuf:='1';
if hcount>1015 then
fiforden<='0';
dtmgbuf:='0';
end if;
end if;
if hcount=1055 then
hcount<=0;
vcount<=vcount+1;
end if;
end if;
if vcount<2 then
vsync<='0';
else
vsync<='1';
if vcount>33 then
displayen<='1';
dtmgenable:='1';
if vcount>513 then
dtmgenable:='0';
displayen<='0';
if vcount=525 then
vsync<='0';
vcount<=0;
end if;
end if;
end if;
end if;
dtmg<=dtmgbuf and dtmgenable;
end if;
end process dotout;
--SRAM读入disfifo控制
disfifocontrol:process(clk60m0,reset)
begin
if reset='0' then
hcount2=0;
elsif faling_edge(clk60m0) then --负沿控制fifowren防止与clk60m0竞争，clk60m正沿作为fifo写时钟
hcount2<=hcount2+1;
if hcount2<400 then
fifowren<='1';
else
fifowren<='0';
end if;
end if;
end if;
end process disfifocontrol;
--SRAM读地址控制
sramaddrcontrol：process(clk60m90,reset)
begin
if reset='0' then
sramoe<='1';
ramaddrout="000000000000000000";
rdaddr<=1;
rden<='1';
elsif rising_edge(clk60m90) then
if hcount2<400 then --这段时间内数据从SRAM读入FIFO
rden<='1';
ramaddrout=conv_std_logic_vector(rdaddr,18);
rdaddr=rdaddr+1;
end if;
if rdaddr>384000 then
rdaddr<=0;
else --这段时间内留给FIFO写入SRAM
rden<='0';
null; --代码待加
end if;
end if;
end process sramaddrcontrol;
end Behavioral;
begin
process(h0,v0,x,y,clk,rst)
begin
if rst='0' then
addrorg<=conv_integer(v0)*800+conv_integer(h0);
xoffset<=0;
yoffset<=0;
addrtemp<=addrorg;
endflag<='0';
elsif rising_edge(clk) then
if not(yoffset=y) then
if xoffset<(x-1) then
xoffset<=xoffset+1;
addrtemp<=addrtemp+1;
else
xoffset<=0;
addrtemp<=addrorg+800*(yoffset+1);
yoffset<=yoffset+1;
end if;
else
endflag<='1';
end if;
addr<=CONV_STD_LOGIC_VECTOR(addrtemp,19);
end if;
end process;
end Behavioral;
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