AT32F4系列外部时钟。

官方给的例程外部晶振默认为8M，若用户自行设计硬件采用25M晶振，代码中#define HSE_VALUE               ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */，如何倍频到240MHZ，倍频参数，分频参数在哪儿设置

at32f403a吧，直接算拿库函数改改就是比如原来240/8=30，现在改为25MHz的话，类似操作就行，把hse除频后再倍频

084425 发表于 2020-8-4 23:15
at32f403a吧，直接算拿库函数改改就是比如原来240/8=30，现在改为25MHz的话，类似操作就行，把hse除频后再 ...

我要问的是倍频系数在哪儿，分频系数在哪儿我只找到了具体到PLCK的分频，没到找晶振PLLM这些PLLQ这些

RCC_CFG_PLLMULT60，就是60倍频的~

雅特力AT32F403A系列是支持HSE/2/3/4/5分频的，采用25 MHz外部晶振倍到240 MHz的话，HSE 5分频后再48倍频即可。240MHz = 25MHz / 5 * 48。
可以在BSP中system_at32f4xx.c文件中找到SetSysClockTo240M时钟配置函数，按如下加粗部分的修改
static void SetSysClockTo240M(void)
{
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  /* Enable HSE */
  RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
    StartUpCounter++;
  }
  while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  }
  if (HSEStatus == (uint32_t)0x01)
  {
    /* HCLK = SYSCLK */
    RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
    /* PCLK2 = HCLK/2 */
    RCC->CFG &= 0xFFFFC7FF;
    RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
    /* PCLK1 = HCLK/2 */
    RCC->CFG &= 0xFFFFF8FF;
    RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
    RCC_HSEDivConfig(RCC_HSE_DIV_5);
    /*  PLL configuration: PLLCLK = HSE/5 * 48 = 240 MHz */
    RCC->CFG &= RCC_CFG_PLLCFG_MASK;
    RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT48 | RCC_CFG_PLLRANGE_GT72MHZ);
    /* Enable PLL */
    RCC->CTRL |= RCC_CTRL_PLLEN;
    /* Wait till PLL is ready */
    while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
    {
    }
    RCC_StepModeCmd(ENABLE);
    /* Select PLL as system clock source */
    RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
    RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
    /* Wait till PLL is used as system clock source */
    while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
    {
    }
    RCC_StepModeCmd(DISABLE);
  }
  else
  {
    /* If HSE fails to start-up, the application will have wrong clock
         configuration. User can add here some code to deal with this error */
  }
}