- void TIM1_pwm_init(void)
- {
- //pin mux
- RCC->AHBENR |= RCC_AHBENR_GPIOB; //enable GPIOB clock
- //B14->TIM1_CH1
- GPIOB->CRH &= ~(GPIO_CNF_MODE_MASK << GPIO_CRH_CNF_MODE_14_Pos);
- GPIOB->CRH |= GPIO_CNF_MODE_AF_PP<< GPIO_CRH_CNF_MODE_14_Pos;
- GPIOB->AFRH &= ~GPIO_AFRH_AFR14;
- GPIOB->AFRH |= (GPIO_AF_MODE7 << GPIO_AFRH_AFR14_Pos);
- //B13->TIM1_CH1N
- GPIOB->CRH &= ~(GPIO_CNF_MODE_MASK << GPIO_CRH_CNF_MODE_13_Pos);
- GPIOB->CRH |= GPIO_CNF_MODE_AF_PP<< GPIO_CRH_CNF_MODE_13_Pos;
- GPIOB->AFRH &= ~GPIO_AFRH_AFR13;
- GPIOB->AFRH |= (GPIO_AF_MODE2 << GPIO_AFRH_AFR13_Pos);
- //init timer1
- RCC->APB2ENR |= RCC_APB2ENR_TIM1;//enable clock
- TIM1->PSC = 71;// 71+1
- TIM1->ARR = 50;// 50us
- TIM1->DIER |= TIM_DIER_UIEN;//enable update interrupt
- TIM1->CCR1 = 25;//duty
- //oc1 configure
- TIM1->CCMR1 &= ~TIM_CCMR1_CC1S;//output
- TIM1->CCMR1 |= TIM_CCMR1_OC1FE;
- TIM1->CCMR1 |= TIM_CCMR1_OC1PE;
- TIM1->CCMR1 |= TIM_CCMR1_OC1M_PWM1;
- //output control
- TIM1->CCER |= TIM_CCER_CC1EN;
- TIM1->CCER &= ~TIM_CCER_CC1P;
- TIM1->CCER |= TIM_CCER_CC1NEN;
- TIM1->CCER &= ~TIM_CCER_CC1NP;
- //TIM1->CCER |= TIM_CCER_CC1NP;
- //set dead time
- TIM1->CR1 |= TIM_CR1_CKD_DIV4;
- TIM1->BDTR |= 36;// 2us
-
- TIM3->CR1 |= TIM_CR1_ARPE; //ARPEenable
- TIM1->CR1 |= TIM_CR1_CEN;//counter enable
-
- TIM1->BDTR |= TIM_BDTR_MOEN;//主输出使能
-
- NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn,1);
- NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);
- }
-
- void TIM1_BRK_UP_TRG_COM_IRQHandler(void)
- {
- if(TIM1->SR & TIM_SR_UIF)
- {
- TIM1->SR &= ~TIM_SR_UIF;
- LED1_TOGGLE;
- }
- }
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