/*************脉冲发生器, 100hz_2路互补****************/
/*************EPM240T100C5N************************/
/*************ID:共同学习FPGA***********************/
/*************20250715*****************************/
//系统时钟100Mhz,设定频率100k,定时时间0-511个脉冲,死区时间32个脉冲;
//B+----------------------------------
// | | | |
// s1| s3| S5| s7|
// |---L1---| |---L2---|
// s2| s4| S6| s8|
// | | | |
//B-----------------------------------
//num |0___________________511|
//num |__________50%__________|100%
//num |12345|6789a|12345|6789a|
//L1 |___0-255___|___________|
//L2 |___________|_256-511___|
//s1 |¯¯¯¯¯|_________________|
//s2 |_____|¯¯¯¯¯|___________|
//s3 |_____|¯¯¯¯¯|___________
//s4 |¯¯¯¯¯|_________________|
//s5 |___________|¯¯¯¯¯|_____|
//s6 |_________________|¯¯¯¯¯|
//s7 |___________|¯¯¯¯¯|_____|
//s8 |_________________|¯¯¯¯¯|
`timescale 1ns/10ps
module maichong
(
clk, //系统时钟100MHz;
res, //复位信号,低电平有效;
s1, //桥臂1上管;
s2, //桥臂1下管;
s3, //桥臂2上管;
s4, //桥臂2下管;
s5, //桥臂3上管;
s6, //桥臂3下管;
s7, //桥臂4上管;
s8 //桥臂4下管;
);
input clk;
input res;
output reg s1;
output reg s2;
output reg s3;
output reg s4;
output reg s5;
output reg s6;
output reg s7;
output reg s8;
reg[8:0] num; //计数器;
reg[8:0] power; //功率;
parameter siqu =16; //死区时间;
parameter zuixiao =128; //最小数50%-100%;
parameter xiang1 =5; //第一相起始点;
parameter xiang2 =260; //第二相起始点;
`define shu (zuixiao +power)
`define shu_ban ((zuixiao +power) >>1)
always@(posedge clk or negedge res) //计数器
if(~res)
begin
num <=0;
end
else
begin
num <=num +1;
end
/**************************************************/
always@(posedge clk or negedge res) //比较器
if(~res)
begin
s1 <=0;
s2 <=0;
s3 <=0;
s4 <=0;
s5 <=0;
s6 <=0;
s7 <=0;
s8 <=0;
power <=60;
end
else
begin
/**************************************************/ //第一相
if((num >xiang1) && (num <(`shu_ban -siqu) )) //前半个周期
begin
s1 <=1;
s4 <=1;
end
else
begin
s1 <=0;
s4 <=0;
end
if((num >`shu_ban) && ( num <(`shu -siqu))) //后半个周期
begin
s2 <=1;
s3 <=1;
end
else
begin
s2 <=0;
s3 <=0;
end
/**************************************************/ //第二相
if((num >xiang2) && (num <(xiang2 +(`shu_ban -siqu)) )) //前半个周期
begin
s5 <=1;
s8 <=1;
end
else
begin
s5 <=0;
s8 <=0;
end
if((num >(xiang2 +(`shu_ban -siqu)) ) && (num <(xiang2 +(`shu -siqu))) ) //后半个周期
begin
s6 <=1;
s7 <=1;
end
else
begin
s6 <=0;
s7 <=0;
end
/**************************************************/
end
endmodule
/******************testbench of maichong***********/
module maichong_tb;
reg clk, res;
wire s1, s2, s3, s4, s5, s6, s7, s8;
maichong maichong
(
.clk(clk), //系统时钟100MHz;
.res(res), //复位信号,低电平有效;
.s1(s1), //桥臂1上管;
.s2(s2), //桥臂1下管;
.s3(s3), //桥臂2上管;
.s4(s4), //桥臂2下管;
.s5(s5), //桥臂3上管;
.s6(s6), //桥臂3下管;
.s7(s7), //桥臂4上管;
.s8(s8) //桥臂4下管;
);
initial
begin
clk <=0;
res <=0;
#20 res <=1;
#10000 $stop;
end
always #5 clk <=~clk;
endmodule
/**************************************************/
/**************************************************/
/**************************************************/
/**************************************************/
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楼主
