代码如下,实现的是数码管显示的代码:
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- Entity smg is
- port
- (
- Clock: in std_logic;
- Input_value: in integer range 0 to 9; --input data
- En: out std_logic_vector(7 downto 0);
- Display: out std_logic_vector(7 downto 0)
- );
- end smg;
- Architecture Decoder of smg is
- --Signal Counter: Integer range 0 to 7;
- Begin
- process(clock)
- Variable Num:Integer range 0 to 9;
- Variable Counter: Integer range 0 to 7;
- Begin
- if falling_edge(Clock) then
- if Counter = 7 then
- Counter :=0;
- else
- counter :=Counter + 1;
- end if;
- case Counter is --Duan xuan
- when 0 =>
- En <= "11111110";
- Num := Input_value;
- when 1 =>
- En <= "11111101";
- Num := Input_value;
- when 2 =>
- En <= "11111011";
- Num := Input_value;
- when 3 =>
- En <= "11110111";
- Num := Input_value;
- when 4 =>
- En <= "11101111";
- Num := Input_value;
- when 5 =>
- En <= "11011111";
- Num := Input_value;
- when 6 =>
- En <= "10111111";
- Num := Input_value;
- when 7 =>
- En <= "01111111";
- Num := Input_value;
- end case;
- case Num is --Wei Xuan
- when 0=>
- Display <= X"FC";
- when 1=>
- Display <= X"60";
- when 2=>
- Display <= X"DA";
- when 3=>
- Display <= X"F2";
- when 4=>
- Display <= X"66";
- when 5=>
- Display <= X"B6";
- when 6=>
- Display <= X"BE";
- when 7=>
- Display <= X"E0";
- when 8=>
- Display <= X"FE";
- when 9=>
- Display <= X"F6";
- when others=> --貌似这里没起作用
- Display <= X"00";
- End case;
- End if;
- End Process;
复制代码
最后一个others好像没起作用,四个位表示BCD码输入 输入0到9显示是正常的。但是只要超过9就乱了,
按道理有了最后一个others约束应该输出的是全灭。但偏偏不是,所以很疑惑。
麻烦路过的过目下,谢谢!!
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